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Found this: which points to: https://www.reenigne.org/misc/ntsc.zip which exists on GitHub at: https://github.com/reenigne/reenigne/tree/master/ntsc It has two command line executables avi2ntsc.exe and ntsc2avi.exe. ntsc2avi.exe converts 8 bit PCM 14.318MHz sampled composite video to AVI...

A normal inductor won't work? https://en.wikipedia.org/wiki/Inductor The schematics say L2 (connected to -12V) is 27µH L1 (connected to +12V) and L3 (connected to +5V) are 28 µH (toroid) These three are connected to the Power connector J7 Actually, I think that's the schematic for the main...

Why do I want AFP? Why don't I have AFP already? When did I stop having AFP? I have Intel Macs (Mac OS X10.4 to 15.0) and PCs (Linux/Windows). I have PowerPC Macs that can run System 7 to OS X 10.5. They can connect to Intel Macs that are running early versions of Mac OS X (either booted or in a...

The way I think an arbiter works is, it checks for REQ from a device and gives it GNT to allow the device to do work. When the device releases REQ, the arbiter releases GNT and checks the next device. I suppose the PCI Local Bus Specification will explain it - at least the PCI part. There's...

Is there a download link for the ROM? I don't think the archive sites have that one. It might be nice to try and emulate it in DingusPPC. I'm looking for any Mac ROM that's not in the list at...

It does simplify things. What ROM does it use? Does it have Open Firmware? The S900 uses the same ROM as the Power Mac 7200&7500&8500&9500 v2 which doesn't have issues with PCI-PCI bridges. There's an S900 discussion at...

You didn't connect an interrupt for E1 so the mouse freezes if you move the cursor onto the GPU that is in that slot. The default interrupt for E1 is the COMM_SLOT_INT. Slot E1 is IDSEL AD17. The interrupt bit is 0x16. I expect you could connect any number of cards and read config data or setup...

I said the interrupts were probably ok for A,B,C because there's an interrupt pin on OHare for each of them. Its the GNT and REQ for C that I'm wondering about. Did you find out if A19 and B10 are connected to anything?

I think interrupts should be working, so you can move the mouse around the display connected to slot C. Does the Matrox card enable bus master? Does it have 2D or 3D acceleration? Try a ATA or USB or FireWire or SCSI card? Some of those probably won't work.

Equivalent in this case means that CSII has the same number of interrupt connections to OHare as Slot_B, just like every other PCI device connected to OHare. Equivalent doesn't mean that CSII and Slot_B uses the same interrupt. All PCI devices connected to OHare have a separate interrupt input...

Is the riser that is the same for Alchemy and Gazelle a two slot riser or a three slot riser? That C600 UMAX Riser is not the same as the Apple Alchemy and Gazelle riser as it has a non-PCI connection with many more pins to accomodate the third slot and a comm slot. I suppose any riser with...

U23 is the chip on Alchemy. You want U20 on Gazelle. Or am I confused about what machine the goal of these threads are for? We don't have Alchemy schematics. U20 is used for doing GNT for 4 of the 5 PCI slots/devices from OHare (page 7-B7). U20 is a 74F32 which only has 4 OR gates so it can only...

I believe bus masters use REQ and GNT (check the PCI local bus specification). What REQ and GNT lines are you planning to use from OHare for Slot_C? Heathrow for Gossamer appears to have 6 pairs of REQ/GNT lines. A bus master is one that can read and write to the Mac's RAM using DMA or read and...

The schematic for J8 of the 6500 says the reserved pins are for a PCI adapter card. I suppose the PCI adapter card is an Apple specific adapter so it can do weird stuff like requiring reserved pins to handle separate interrupts. Where's the schematic for the riser (PCI adapter card?)? Are you...

Every slot has 4 interrupt pins A,B,C,D. These may be reordered per slot. Usually a PCI card uses int A. Int A may be connected to int A or B or C or D on the motherboard or riser because of the reordering. A multifunction card may use more of the interrupt pins (A,B,C,D). None of that matters...

All bridges have the same access. I don't have a ROM with Open Firmware code that mentions a bridge 3. Maybe it exists in an Apple Network Server? Or some kind of prototype machine? Bridge 0 is usually @F000000 Bridge 1 is usually @F200000 Bridge 2 is usually @F400000 Bridge 3 is usually @F600000

Apple II question: Does it draw even and odd fields of an NTSC frame? Can VBL be detected? If yes to both, then wouldn't it be possible to create a 280x384 interlaced mode by switching between HGR and HGR2 at 60Hz? Then you could have a 560x384 mode by switching between DHGR page 1 and DHGR...

Did you check the Apple Developer Discs? Maybe 1995 Reference Library discs: https://archive.org/download/Apple_Developer_Discs_1989-2009/1995/Reference%20Library/

The Apple //jse GL Renderer seems to do color fringing more accurately than Virtual ][ (at least according to my expectations for my test image A - the pink and aqua columns on the right side are mostly a single color).

I tried A2D using Apple //jse. I don't think A2D supports loading lores or double lores images? A2D loads HR as DHGR. You can tell by moving the mouse which makes the cursor visible. The cursor is definitely using DHR pixels. The HGR image is loaded into the main column of DHGR immediately. You...