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  1. M

    68k Fun with Filemaker Pro 3 retro development

    How easy was it to import the text in the first place and structure it appropriately? How was the source data formatted, and did you need to do much massaging to fit the desired database structure?
  2. M

    WarpSE: 25 MHz 68HC000-based accelerator for Mac SE

    My point (which I probably muddled), was just that I’m skeptical there’s much of a market for replacement SE ROMs, other than maybe as a repair part. Clearly that’s just my opinion, and I don’t have any data one way or another to back it up. That said, it sounds like it would be the same...
  3. M

    WarpSE: 25 MHz 68HC000-based accelerator for Mac SE

    Hmm… if the SWIM weren’t required separately - maybe? With the SWIM I feel like you’re talking $50-60+, plus the cost of a SuperDrive. Generally speaking, I feel like you’re going to have two camps: 1. Folks that are generally content with the machine as-shipped (or prefer the original...
  4. M

    68k Fun with Filemaker Pro 3 retro development

    Cool! Looks like really good work! Seems like you put together a nice framework for this type of application/database.
  5. M

    WarpSE: 25 MHz 68HC000-based accelerator for Mac SE

    Thinking about this some more, you could also do dynamic adjustments to the refresh probability - every time you don’t opportunistically refresh but could have, you increase the refresh probability; every time you do opportunistically refresh and shouldn’t have, you decrease the probability. You...
  6. M

    WarpSE: 25 MHz 68HC000-based accelerator for Mac SE

    It’s probably possible that you could do a statistical analysis of the ROM to determine which percentage of instructions will touch RAM on the following access - loads, stores, operands in RAM (based on the addressing mode), etc. You could then tune a refresh strategy based on the likelihood of...
  7. M

    IIci with no SCSI

    Those will probably be connected back to the CPU or the Memory Decode Unit, but I’m not sure which. SEL is the chip select so that the SCSI chip knows the CPU is trying to talk to it, and DACK (Data ACK) signals back to the CPU that the CPU read/write to the SCSI chip is complete.