Here's my latest design for a Mac IIfx RAM SIMM. As always, it's a collaboration with Garrett Fellers and open-source even for commercial use if you remove the Garrett's Workshop trademark. Now, unfortunately I don’t have a IIfx so I will need some help testing these once I get em. My rule is that I must have a relevant gizmo almost finished before I can buy a new model of vintage computer haha.
Source: https://github.com/garrettsworkshop/MacIIfxRAMSIMM
Pictures:
Front address bus routing:
Inner layer with data bus, little bit of address bus:
This is actually my second attempt at a IIfx RAM SIMM. This time I am using eight 16Mx1 RAM chips per SIMM totaling 16Mx8 (16 megabytes) and the design is really straightforward.
The first time I did a IIfx RAM, I wanted to use just two 16Mx4 chips to lower the cost. I had a design that looked like this:
It's got two RAM chips plus two 74ACT244 buffers and a bunch of little logic chips which are supposed to convert the peculiar IIfx RAM pinout, designed for eight separate chips, into signals compatible with a 2-chip array. Unfortunately this design might work but might not. There is a particular behavior which this SIMM just doesn't do correctly, a non-fast-page-mode read-modify-write cycle.
For the technically inclined, a non-FPM RMW cycle is where the RAM controller brings /RAS and /CAS low as in a regular read cycle, reads from the data bus, then negates /OE, drives write data on the bus, and pulses /WE, all without ever releasing /CAS. Contrast with a FPM-type RMW cycle where there are two /CAS pulses.
So long story short, I don't know if the IIfx does such a RAM access cycle, but if it does, the 2-chip SIMM won’t work properly. Therefore I abandoned the two-chip approach. I could do a 2-chip design with FET switches, I think, but then it would be almost as expensive as the 8-chip design. So the two-chip design was abandoned and I went back to the easy, straightforward 8-chip design.
Anyway, I also have this adapter which should let me test the IIfx RAMs (one at a time) in a commodity 30-pin SIMM tester:
This adapter basically undoes the separate read and write buses of the IIfx RAM. Therefore the test coverage isn’t perfect since the adapter shorts the read/write buses together (as they are on a 30-pin SIMM) so the tester can’t check for shorted read/write data pins on the SIMM under test. Fortunately those are on opposite sides of the RAM chips so it would be really hard to short ‘em. The main purpose of this thing is to let me get confidence in some SIMMs before sending them out to a tester.
Who would like to test? Admittedly I have a big project backlog so it might be a month or two before I get it all together... I just wanted to get this design out there on GitHub and post this explanation in the meantime.
Nevertheless I must eventually acquire a IIfx, at least just a board—that was the whole point of the RAM for me haha. Onto that…
Source: https://github.com/garrettsworkshop/MacIIfxRAMSIMM
Pictures:
Front address bus routing:
Inner layer with data bus, little bit of address bus:
This is actually my second attempt at a IIfx RAM SIMM. This time I am using eight 16Mx1 RAM chips per SIMM totaling 16Mx8 (16 megabytes) and the design is really straightforward.
The first time I did a IIfx RAM, I wanted to use just two 16Mx4 chips to lower the cost. I had a design that looked like this:
It's got two RAM chips plus two 74ACT244 buffers and a bunch of little logic chips which are supposed to convert the peculiar IIfx RAM pinout, designed for eight separate chips, into signals compatible with a 2-chip array. Unfortunately this design might work but might not. There is a particular behavior which this SIMM just doesn't do correctly, a non-fast-page-mode read-modify-write cycle.
For the technically inclined, a non-FPM RMW cycle is where the RAM controller brings /RAS and /CAS low as in a regular read cycle, reads from the data bus, then negates /OE, drives write data on the bus, and pulses /WE, all without ever releasing /CAS. Contrast with a FPM-type RMW cycle where there are two /CAS pulses.
So long story short, I don't know if the IIfx does such a RAM access cycle, but if it does, the 2-chip SIMM won’t work properly. Therefore I abandoned the two-chip approach. I could do a 2-chip design with FET switches, I think, but then it would be almost as expensive as the 8-chip design. So the two-chip design was abandoned and I went back to the easy, straightforward 8-chip design.
Anyway, I also have this adapter which should let me test the IIfx RAMs (one at a time) in a commodity 30-pin SIMM tester:
This adapter basically undoes the separate read and write buses of the IIfx RAM. Therefore the test coverage isn’t perfect since the adapter shorts the read/write buses together (as they are on a 30-pin SIMM) so the tester can’t check for shorted read/write data pins on the SIMM under test. Fortunately those are on opposite sides of the RAM chips so it would be really hard to short ‘em. The main purpose of this thing is to let me get confidence in some SIMMs before sending them out to a tester.
Who would like to test? Admittedly I have a big project backlog so it might be a month or two before I get it all together... I just wanted to get this design out there on GitHub and post this explanation in the meantime.
Nevertheless I must eventually acquire a IIfx, at least just a board—that was the whole point of the RAM for me haha. Onto that…
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