Recent content by trag

All plastic and rubber or silicon. I got my set from Amazon, more or less by mistake, but found I really liked them. I ordered a set of spatulas that looked completely different that I'd had in the past, and the ones in the link above are what they sent me. Of course, that Amazon seller...

Thank you, for your kind offer. So it looks like about 60 eu. to buy the six sets, plus 12 eu. in shipping to get them to you. My address is: Jeff Walther 8107 Hillrise Dr. Austin, TX 78759 What would be the cost to ship them to me in the USA? Will PayPal be okay for sending you the...

Anyone willing to purchase six sets of these and ship them to me in the USA? For some reason this seller will not ship to the USA. https://www.ebay.com/itm/394791001619 I have a set I'm very fond of, but after years of use, their edges are starting to fray a bit.

That looks very similar to the 6809 development board we used in my Machine Code programming class back around 1982.

I wonder if this is an artifact of using the same ROM on both the PowerSurge and Catalyst machines. PowerSurge doesn't support greater than 64 MB per bank (although the HDN details suggest otherwise) and no noe could build such a DIMM back then, so why bother to write in support for greater...

Looking through the Hammerhead and Platinum documents carefully, they strongly suggest that banks are controlled on a /RAS basis, however, Hammerhead is weird. Each pair of DIMM sockets gets the same two /RAS lines. This makes perfect sense, I think, when the machine is operating in...

Just started reading, but the Platinum ERS document states right up front that it supports up to eight, 128 MB banks of RAM on four DIMMs.

The schematics show the wiring, but not the behavior. I've also crawled through the Hammerhead ERS document and it does not shed light either. I suspect the necessary information might be in the JEDEC standards for the supported DIMMs. Thank you for the suggestions though. Are you able to...

So I understand that 72 pin SIMMs use the /RAS signals to distinguish between and separately activate different banks. How is this done on the 168 pin FPM DIMM? There's a Bank signal, B0 on the DIMM, but the 9500 HDN claims this is tied to A0. The 9500 lists four /RAS lines, suggesting two...

I checked System Profiler on the machine I have here with a 6280M installed and it also shows Vendor 1911, 9 and Revision 2. So I don't think there's any useful information there.

Thinking, but nothing comes to mind. Recheck Bbraun's instructions. My very vague memory from 20 years ago says there was more than one resistor pair to move, but that is not a relible memory and I would expect Bbraun to be thorough.

I am informally, in my head, targeting the end of the Summer to have an (externally) programmable ROM module available. This may affect considering a fix in ROM. As a fair disclaimer, I should point out that it took me twelve years to finally finish the PEx ROM project. But I'm not...

You are a PLD deity, Bolle.

I'm looking at the caches on Fizzbinn's excellent guide: https://tinkerdifferent.com/resources/ppc-macintosh-l2-cache-modules.19/ Specifically in the last category for PowerSurge and Catalyst machines: D - 7200/7300/7500/7600/8500/8600 160 pin Cache DIMM Pin groupings: 25 - 35 - 20...