Recent content by Zane Kaminski

SDRAM is not that bad. 15 address pins plus CS, RAS, CAS, WE, CKE, and then the clock which might come from an oscillator or your FPGA. So 20-21 extra pins on the FPGA are required if it’s already connected to the full 68k address bus.

Oh also @Melkhior, regarding flushing the cache, I suggest doing it differently. When a cache flush is initiated, the cache will be disabled for some time. During this time, the FPGA iterates through the cache memory and invalidates each line. Maybe you have to acquire the bus to do this, in...

Just do a small tagged SRAM cache in the FPGA and then use (S)DRAM for the main memory instead of SRAM. 30 EUR is a lot for RAM. It’d be better to spend that on a larger or faster FPGA. For reference, I just bought a few hundred RAM chips for the production batch of the WarpSE and paid less than...

Ah got it. Surface mount is so much easier for us than through hole since we can basically do it automatically. Only thing I’ve learned to not do as surface-mount is the PLCC sockets for the CPU and flash ROM. It’s better to use through hole sockets for those surface mount components. If there’s...

Like this?

Small update. As I mentioned earlier, the first 15 prototypes of the WarpSE require a few mod wires on the board between some of the socketed chips including the MC68k CPU. The first prototype used large diameter modwire but this prevented us from installing the CPU and ROML sockets: We want...

I think for a first pass we oughta omit DMA support since plenty of cards are just slaves. The bidirectional ‘646 and ‘651 registers/latches used in the Mac II NuBus implementation are quite expensive these days. They are more than twice as much as unidirectional buffers or latches. It would be...

Beware, it may not be pin-compatible. Instead of repurposing old NuChips, we should just reimplement it. I wrote out the bus timings for a non-DMA-capable 68030-to-NuBus adapter a long time ago. It was quite easy to do and the whole design required only XC95144XL CPLD and 12 74AHCT574 register...

It's not too hard to do the bus mastering. For example the WarpSE's CPLD is already a sophisticated enough bus master. The 7.8336 MHz PDS master signaling/timing is totally done by the CPLD. None of the fast 68k's signals go directly to the bus. There are a bunch of fairly complicated logic...

That’s why my aim is to build up single-function gizmos which are halfway well documented and work really well. Once I have enough of those I can combine them into an all-in-one thing. Semi-relatedly, did you know that the IIsi and IIci chipsets support a burst write to RAM? 68030s can only do...

@Trash80toG4 tbh I don’t really understand the purpose. It’s quite a lot of work to do the mod you’re proposing. Maybe we should just make an accelerator for the IIsi with 128 MB onboard RAM lol. 40 MHz sounds good enough as long as it’s paired with a fast burstable RAM system and some L2 cache...

Maybe we’re confusing bank A and B. When I say bank A I mean the soldered RAM used for video. Bank B is the SIMM slots. So yeah, you can get all those signals on the pads of the bank A chips, but it’s like 50 things you need to connect to. Is that what you mean?

Nope, all the bank A and bank B RAM array pins are totally separate. And it makes sense if you think about it. If the bank A address or data bus were connected to the bank B chips, how could bank A be doing video stuff while bank B is concurrently serving the 68030? All the pins are separate and...

Now wait a minute here. I fear I have created a monster lol—there is no reason to do this mod! It’s a dumb idea! It makes your IIsi slower!! At the highest supported resolution and color depth, the motherboard RAM in bank A is almost 3x slower than the bank B RAM. As others have said, it’s best...

Yeah, you can put a double riser card in that accommodates an accelerator and an Ethernet/video card. It’s tight but it can be done