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NEW APPROACH ____________________________________________________ A straight up 1:1 clone of the FPD card in wire wrap in the form factor of a standard SE PDS Card is what I'll start doing. Documenting the schematic one wrap at a time. - cloning the card is pointless, even though it's the only...

Dang, jumped the gun again and in the wrong direction. Got a few days out of town. Guess I'll be buzzing out the entire front end of the card before looking into anything else? I'm trying to eliminate the card entirely as the final step in FPGA development. Treating the front end like it's the...

Not even close to that yet, running out of town for a bit. Knocked together PDF 14 and attached it above, heading all serial related lines toward Pi rather than VRAM input lines, going with alternate approach you guys suggested upthread. edit: looks like tags are a pin too high on the right...

Clean slate. So it goes . . .

Got it, comparison to simple DRAM shook something loose in my noggin, thanks Looking into switching gears to capture serial output of frame redraw to "Back End" of the card. Same carrier board, whole new approach to VRAM I/O. Heading out of town, will be doing my doodling in #2 pencil on paper...

Incremental updates I understand, Data in VRAM iis refreshed when it's accessed, so it remains the same until actively changed by the CPU and not everything needs to be changed for every frame. CPU reading data back from VRAM makes no sense at all to me, by what mechanism is that accomplished...

Don't understand why feedback is required for scrolling, pointer movement and such. CPU knows it's scrolling and feeds the next frame to VRAM accordingly, no?

Hoping it will. Thinking at work today, I've decided to map the card from the PDS connector on the MagicBus Card, pretending that four row monstrosity is not even there. So I'll be modeling FPGA Card V.1 and markup/schematic takeoff will be a lot simpler task. Also will breakout any PDS signals...

Just read my last and it was badly worded. Not cutting off discussion until testing is done, just saying my responses will be delayed and fewer while off to see the GRLF Don't get much time on the forums. Here's a better representation of Rev.1 in SE PDS Card form factor: Got ahead of myself...

Not cloning the card actually, just the first few parts of its front end that feed Page Buffer data input to FPGA in place of VRAM. No need for VRAM at all, just ROMs and probably that one GAL will be on the Rev.1 board as in the diagram above. The point would be using the existing Radius...

COOL! Didn't know that'd be possible. I've been wondering about doing something on the order of a MacPaint program with a full screen 864x640 canvas to play around with mapping pixels. Doing it visually, comparing baseline screen output with what the Pi is doing might be fun for a bit and then...

Yep it's mapped to the PDS Slot's address space, but the buffer data will be in VRAM and inaccessible to the CPU for all practical purposes, no? VRAM outputs don't head back to the CPU, no need for that at all on a VidCard. Indeed, I just grayed out the extraneous bit about Vampire Video and...

Interesting, but the Page Buffer is built up in VRAM sequentially in alternating cycles split with other CPU activity. AFAIK it never exists as a whole on the system board, that's what VRAM is for after all. Not sure you'd be able to capture the Page Buffer from a Vampire Video subsystem on the...

Can't see the traces yet. I need to test this card, the one I got recently was listed as tested good and will be set up first with output running through the Extron Scaler. Then on to the original board. After it tests good, I'll be de-soldering VRAM. I'll get a good pic of the traces under...

Pi Zero's been approved as a good proof of concept platform. Just checked, Pin 5 is a data line and not tied together. Wouldn't expect them to be. Haven't looked at data lines yet, why do you ask? As a first step, I want to use Pi in parallel input mode to sort out data line load order for...

Bad news just got worse from the serial output point of view, but maybe a whole lot better from mine? Pretty much verified the confusing first findings and buzzed out another mystery after poking at the lines you asked about. SOE is tied together as well! Guessed I'd be finding something...

I'll give it a shot: That's pretty much it, butPi Zero 2 W will probably only do "every so often frames" which may or not be rotated. Pi 5 with 4x Cores/2.4x Clock might be able to do it? Ultimate goal is taking the project to FPGA, much as in the PCB Representation I just did. In that full...

I guess I should explain the point of the overly complicated wire wrap prototype. Aiming toward doing a PCB set up like so. To run the adapter sans VRAM, only the sense line on the board's connector needs to be shorted. Likely will need to be shorted to run output from the connector/cable...

Need some advice from you digital circuit design guys. GPIO advice would be much appreciated as well. Will divining the load order of the Data lines be practical in the parallel input mode? They're related to the addressing inputs, but that seems like a lot more programming if possible at all...