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WD-40 is a bit too lube-y. Solvalene sounds interesting! I had never heard of it. Contrary to the "-lene" suffix it's water-based. But Zep is fine, just make sure to get it pretty hot in the ultrasonic or else the cleaning action is slow and it screws up the board by the time it’s clean. At 85...

I'm working on some hardware with the RP2040 and supporting equipment. The design is in the same form factor as my previoius Mac SE video/power adapter: Of course that gizmo doesn't do line rate conversion, hence the motivation for the Pi Pico/RP2040-based design. Major parts in the new...

Yes, many times over. It often doesn't really wash the flux off, just sort of pushes it around the board. Plus it's expensive compared to water and degreaser. Also don't use 99% (i.e. anhydrous) isopropanol to clean a MacBook keyboard. It wicks up the sides of the keys and weakens the plastic...

Sort of. That's the result of being in 85 degC Simple Green solution for an hour. The reason for this was that we couldn't find our preferred cleaning agent, Zep Industrial Purple Degreaser. So we tried Simple Green, ostensibly a similar product. Most important thing about the choice of cleaning...

Garrett just fixed the video gizmo with a new bodge circuit: And now the video is working on the multisync LCD: Sort of. Guess this Mac SE board is messed up. Gotta fix that and then we can continue. Edit: That was easy. Just had to jiggle the SIMMs a bit.

Nope, it takes regular 30-pin SIMMs

Garrett just finished the rest of the assembly of some WarpSE prototypes: I’ve gotta redo the clock switching and DIP switch logic as I mentioned a while ago, then I can try it out!!!! :D

Finally we have gotten through our very long production and prototyping backlog enough to made a batch of 50 of these! They’re going in the oven right now. Then of course we need to inspect, do any rework (shorts, etc.), hand solder on the connector, quick test, rework+test again if...

Sounds like it's time to do a board! I can modify my SE ATX+VGA adapter for the purpose. As for feeding the constants, let's try to have one loop on the second core that services all of the real-time stuff: feeding the constants, retrieving the video data, and constructing the output...

Here's my thought about the PIO program to implement what I described. The limitations of the PIO make it difficult to load a constant greater than 31. These values have to be sent from the ARM to the PIO via the FIFO lol. Clumsy but it does have some benefits. ; acquireline gets HSYNC low ->...

Uncompensated, the 0.2336 MHz truncation will make the sample point will drift later and later, eventually skipping a whole pixel somewhere on the screen and instead capturing the 513th pixel which is always black. Yeah, that would be disastrous although as we have discussed before, there are...

Hmm okay there is one gotcha. The issue is that the RP2040/Pico's PLL can't actually do 130.2336 MHz. 130 MHz is as close as we can get. Unfortunately at 130 MHz, it's difficult to get the divided PIO clock frequency accurate enough to not drift over one line. At 130.2336 MHz, the division ratio...

Yeah although it’s a bit overkill since we only need 1-bit video at a fixed resolution. PicoVGA supports colors and sprites and all sorts of other stuff.

Okay I have it worked out pretty good for 1024x768 VGA. For 1024x768, that’s a 65 MHz pixel clock. So let’s clock the system clock at approximately 130 MHz. PLL can’t always synthesize the exact frequency required and also we want to tweak it to line up better with the Mac’s pixel or line...

Ah great, I missed that element of the autopush functionality in the datasheet. I thought that autopush meant to implicitly push at the end of every IN shift operation, as opposed to just when the shift count has been reached after multiple INs. But do keep in mind that the system clock must...

That’s the thing, it will be hard to constrain the alignment properly, and you will certainly have to re-decide on whether to do the extra clock for alignment on a line-by line basis. At 2x pixel clock it’s maybe doable but there are many gotchas. The way the system clock division works is very...

Issue is that although the 256kx4 and 1Mx4 DRAM pinouts match, the pinout for 4Mx4 is different. LC III has eight 1Mx4 chips, making a 1Mx32 array i.e. 4 MB. To go to 16 MB you'd need 4Mx4 chips: 1Mx4 chips as on the LC III for contrast: Look similar but unfortunately the pin count and pinout...

How can you tell during operation whether to add the delay?

Well the XOR gate is just so that I can choose whether to invert the hsync/vsync/video signals with a jumper. As for why they're separate, it's a transmission line effect thing. I wanted to use a both-ends termination where there is a 75 ohm termination resistor not just at the load (monitor)...

Nah, we just have to adjust the PIO divider ratio separately for each of the PIO state machines involved. There are two separate PIO units each with four PIO state machines. I think DVI output uses three or four state machines in one PIO, leaving the others free. Right? And by the way, the way...