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Okay I have looked into the PIO and yeah, it's quite robust. But there is still an issue... We can set the clock divider to approximately the same as the Mac's pixel clock. And then we would want to write a PIO program that does this: But if we are running the PIO at ~15.6672 MHz, then we...

Just to reiterate, here is a scope trace showing the probable reason that the monitor won’t sync correctly: When the HSYNC signal is low, the beam of the CRT is drawn to the left of the screen so as to start scanning out a new line left-to-right. To an LCD’s controller or the DVI gizmo we have...

Oh, huh. Well 133 MHz is much more workable if we have to do the oversampling. And yeah, I think 15.663240 MHz is close enough for one line. Only differs by 11 nanoseconds (i.e. 1/6 of a pixel) by the end of the 704-clock line. But how do we ensure we start the SPI transfer in the proper...

Yeah, or you could adjust the clock on the capture board. But then the temperature would change, etc. and it would go out of tune and the picture on the screen would start shifting or rolling or whatever. So instead you use a phase-locked loop which is basically a frequency...

I think the clocking strategy you're describing actually won't work since you can't divide 48 MHz into the 15.6672 MHz pixel clock. Maybe you can do 48 MHz / 3 = 16 MHz but because there is a frequency difference and therefore no consistent phase alignment, some kind of correction for the...

Yeah, this is basically what I was discussing with alxlab and Androda in the chat transcript in the other thread. The main challenge is not a digital/analog issue but a timing issue. We know the Mac puts out pixels to the analog board at the rate of 15.6672 MHz (i.e. 15.6672 million pixels per...

I think the main issue is that I ignored the HSYNC pulse width problem. The Power R adapters have this little high-pass filter formed by C2 and R2: This limits the pulse width of the HSYNC signal to 2-4 microseconds or whatever, instead of the 20ish microseconds (!) the Mac leaves it on for...

I would say it's not a schematic-heavy kind of project. Regarding the algorithm I described: "Start the SPI [transfer] at the end of the line, wait until the next line, find the hsync transition, go backwards some fixed amount to find the first pixel, then sample each pixel by going forward...

I bought an SE motherboard and hooked it up to the power/video converter thing: No WarpSE connected yet. I just wanna get the display thingy working. Unfortunately none of my displays like the Mac's sync timing. Here was the best I got on my HP L2335: The color is inverted but that's not the...

Yeah, adding more ram isn’t too straightforward. From a hardware perspective it’s easy as you mentioned, just add more RAM and utilize the corresponding address wires. It’s a software problem. The ROM software is programmed with an assumption that devices such as ROM, floppy SCSI, etc. are...

@retr01 Thing about the ScuzzyGraph is, it's quite complicated from a software perspective. The ScuzzyGraph driver intercepts commands sent to Quickdraw, checks if they are destined for the external screen, and if so, packetizes the command and sends it over SCSI to the ScuzzyGraph external...

Yeah, that's usually our aim. Hence why the previous hardware revision of the NuBus WiFi card was rejected. 40 chips! They're all like $0.25 each but we can just use an FPGA instead. We realized a long time ago that we have to do this stuff with the "minimum viable product" approach. We can't...

Long answer if I am to be thorough but I guess I'll write a bunch about a possible “WarpSE/30" since I've been asked so many times in varying levels of detail. A really great accelerator for an '030 system is a difficult project to truly get right. I had the WarpLC partially done six months ago...

Just got the WarpSE prototypes back from JLCPCB! I had most of the parts put on by them but I have to add the 68000, CPLD, RAM, PDS connector, update system crystal, 25 MHz oscillator, 3.3V regulator, and put the ROMs in the sockets. I also have to make a program to rearrange the ROM file before...

Okay last update from me about the Suska core since we can't actually make anything with an FPGA big enough to put it on. Well I was tired last night when I was compiling the Suska core for the Lattice ECP5 FPGA so I didn't think of something obvious. I think in retrospect one possible reason...

@Melkhior I looked for FPGAs that could host the Suska 68K00/10/30L but there's really nothing big enough that's currently obtainable. I know where to get the larger MachXO2 and MachXO3 variants from Lattice but they are still quite small and also expensive per LUT compared to Spartan or...

I might be wrong but I think the general understanding is that Xilinx is EOL'ing a bunch of their older stuff. Spartan-6 has not been officially discontinued but the word people are getting from Xilinx is that its days are numbered. I think the same is true of XC9500XL. Hope not but I had...

Hello and thanks for your interest in the project! Actually I think you might be a bit mistaken. The WarpSE is an all-new design with various architectural features not present in older accelerators like the Performer. I like reproduction board projects like the Mac SE Reloaded and making small...

Yeah, we need something to facilitate probing the board for debugging since it’s pretty hard to access inside the chassis. And also for serial production testing purposes. There’s no dedicated thread for it; I just whipped it up in a day or two. Yeah, and the existing cores aren't really...

@JDW I think one of the important differences in what you’re describing compared to autocorrelation is that autocorrelation is the correlation of a signal to itself, historically. That’s as opposed to the correlation between a signal and some other signal. Like I said, I don’t really understand...