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We can do that and it would be easier but it’s not as fun. The secret sauce is sort of in the Ethernet chip so if you use that it doesn’t feel as open-source, and it certainly wouldn’t as cheap to make. My design has 25 chips but they’re all 7400 series aside from the ESP32 module, ROM...

The accelerator I posted about yesterday is a bit advanced so I figured I'd finally do a schematic for an idea I've had for a while. This one is more softwarey and there are a lot of great software developers out there so hopefully we can get some kind of collaboration going. One of the things...

Hi everyone. I wanted to post about my new design for a 25 MHz 68HC000-based Macintosh SE accelerator. As usual with my gizmos, this is a collaboration with Garrett Fellers of Garrett's Workshop. I'm the principal designer and Garrett is the codesigner and he manufactures our boards. My aim...

Yep, that's the vendor I was referring to. As for the overshoot, I think it's more of a thermal thing. If you've raised up the pin to Vcc+2V or whatever then there's a lot of current flowing and so the ESD diode on the die is heating up a lot. About the EDO-to-FPM conversion, it's easier with...

Yes it’s a bit of this but also there are legit 5V tolerant 3.3V DRAMs. The difference between a 5V tolerant 3.3V DRAM and one that's not is in the input protection circuit. The "classic CMOS" protection circuit is employed on a chip is a set of diodes sort of from ground to the pin and from the...

Yeah it would be better to use the 5V-tolerant 3.3V stuff, then we could eliminate the eight data buffers and all the ugly control stuff but it’s only certain mask revisions that are 5V-tolerant. It’s hard to make sure you’re getting those. But like I said before, $25 each is a hard price to...

Yes! LVT or LVC are fine for the address/control buffer. We need buffers on all the data lines too, so that’s 8 more LVC245s or whatever that are required. The 16244/16245 chips don’t really take any less space and aren’t a great value so I say let’s skip em and use two chips. With 8 data...

Issue is that it only makes an 8 MB DIMM, 16 MB if you do dual-sided placement and put eight on. So the chip cost is $12 for 16 MB and I think that’s above the market price for a 16 MB DIMM. You could put more DRAMs and further decode the /RAS or /CAS signals to get a larger SIMM but then you...

It’s doable but you need eight 8Mx8 chips to make one 64 MB DIMM which are kinda rare. It’s a lot of old pricey RAM. Consider that a 64 MB kit of four 16 MB 30-pin SIMMs is going for $45 and this is not too far above the chip cost. I think at GW we have been paying over $20 just for the chips to...

I don’t think it can really be made with new chips. There are several issues.... For even 70ns FPM DRAM, the fast-page /CAS access time is quite short, 20ns or so. All you have to do to accomplish a fast-page access is to set up the column address on the DRAM address bus, assert /CAS, then wait...

My current angle on this problem (EDIT: specifically for the x100 machines) is to use 3.3V synchronous SRAM plus LVC/LVT buffers (or voltage limiting FET switches if necessary) for the data memory and then implement the entirety of the tag stuff (memory and address compare) in an FPGA e.g...