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I'd be really surprised if you find anything like that, but if you do, please share. I've been considering writing something that hooks up to QEMU's gdb interface; I think that would open up a lot more options compared to attempting something native.

With all due respect to Bolle's great technical work on this project, this is a perfect demonstration of the problems with trying to produce hardware without any margin (i.e. non-commercial licenses). I've seen the rule of thumb to sell at a price of absolutely no less than 2.5x your...

I think the availability for FPGAs is still absolutely awful, very bad year for hardware. I think the esp32 was going to be connected via SPI, so just a few pins, and probably pretty easy to add to an FPGA project.

doesn't the Mac Portable support 9MB? seems like a comparison of the SE and Portable ROMs could be pretty fruitful, especially with the supermario source

it looks like it's just two types of capacitors that are out of stock? switching to some other similar part is probably worth it, the supply crunch in electronics makes actual ship times hard to predict right now. maybe you could try the "B41888C5478M000" and "MAL225090105E3" instead? (not an...

Ok, just read some more code, I think I've found a better spot to mess with, I'll post another attempt once I get it figured out.

all in Ghidra! ...and also referencing the leaked copy of the ROM source code, which helps a lot! I figured out a way to tell Ghidra about Macintosh A traps last night, which makes it go much more smoothly. I put some defails in my repo at https://github.com/cy384/68k-mac-rom-maps I was...

Here it is, set for 16MB. To make it, I flipped that one byte from 1 to 4, and then recalculated the checksum for the ROM.

Found, I think, the right spot in the LCIII ROM, I'll make some tweaked ROMs this evening with different values. I think it has to be multiples of four, do 8, 16, 32 work for you?

the C650/Q650/Q800 hardware supports more, but the stock ROM lacks support for 64MB/128MB SIMMs. With hacks I've booted with a total of 392MB. The ROM code often makes assumptions about what machines max out at, if anyone runs into these for a particular system I can point them to the code.

Once you have the FSSpec for the file, I think you can use the FSpGetFInfo and FSpSetFInfo functions. See "Inside Macintosh: Files" and https://dev.os9.ca/techpubs/mac/Toolbox/Toolbox-464.html#MARKER-9-493

yes, the ROM seems to have a hard-coded assumption afaict it's this snippet does the LC III have a ROM socket? if so, it might be "easy" to change the behavior here with a custom ROM

Yeah, that largely meshes with my understanding of the situation. SCSI chip: is the Z53C8003VSG compatible? seems like Zilog still makes it? Mouser has some, anyway. ADB chip: I've been following the ADB PIC discussion, seems like they're pretty close, maybe one or two mysteries away from...

So while I was doing some other stuff I found out that Apple published a bunch of ROM map files with MPW, which have the addresses in ROM for a bunch of stuff, for all(?) 68k Mac ROMs. I converted them into a format that Ghidra can import, and some quick instructions, you can find them here on...

I'm willing to put up the cash to sponsor someone who wants to implement the hardware for this (the BBU/RAM replacement). I think we as a community are very close to being able to make new Mac SE clones with exclusively modern parts (minus the CRT, plus modern video out, etc.), and I really...

The first four bytes are a checksum, the next four bytes contain the address to start execution. So that's the address to start decoding at. Unfortunately there's tons of data mixed into the ROM, a full disassembly will take a lot of work. I used Ghidra a little to help with my ROM hacks...

Here's what my (somewhat modified) Centris 650 has in that region of memory: It just continues to repeat. The first part (bytes 0 to 5) is apparently the MAC address but with the bit order flipped around (which seems like a weird way to store it???). I don't know what bytes 6 and 7 are, but...

In terms of supporting possibly concurrent access to the card, it seems to me like it would make sense to split the registers/address space between wifi configuration stuff and "ethernet" stuff, which seems like what you're suggesting? So network operations (send/receive) and configuration...

Commented on discord, but also saying it here: if nobody else wants to call dibs, I'm up for working on the ESP32 firmware for this project. Also maybe some other bits, maybe the 3D printed bracket, messing with the DeclROM, etc. Schematic looks nice to me after a brief skim. Is that github...