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James @JDW brings up an important point. I planned on only putting the FDHD ROM in the WarpSE but the later FDHD ROM won’t boot really early system software versions. I didn’t plan on socketing the ROM either. If your motherboard has the original ROM, you can of course disable the WarpSE to fix...

You can also change the pinout of the Xilinx CPLD if you need. Just let me know what your final pinout is so I can make sure it'll fit in the CPLD with the pinout you're using. Edit: Also no need to connect to the Mac's 16 MHz clock since it's not on the 68000. The 16 MHz clock is only used by...

The key difficulty is that the algorithm used to generate the sound is particular to the CPU speed and video/sound output timing. We could fix it in software it but I prefer not to patch the ROM/OS. The issue is that that sound generation algorithm runs too fast and the sound buffer gets...

Yeah, it can be done, but then the installation instructions have to have a “desolder your CPU and solder in a socket” step, which is fairly difficult to do with the large DIP-64 package of the MC68000. It’s also pretty easy to destroy the through hole plating on the motherboard if you pull the...

I've got a fairly complete description of the four-voice sound issue for anyone who's interested in the technical details. I keep talking about it but I never show exactly what I mean with diagrams and stuff. As we all know, video generation in the classic Mac is based on the 15.6672 MHz system...

Yeah that looks better. That way you can easily swap a defective accelerator. We could do this I guess but I think it would be better for someone else to tackle the project. I should do a whole new architecture of accelerator for the SE/30 or something rather than re-laying out this thing for...

I don’t think so—that’s the reason I don’t wanna sell a Plus accelerator. I usually want my gizmos to be really easy to install and use. I feel like having to solder it on or whatever just makes it too hard for a lot of people and also hard to support paying customers. Like, Big Mess O’ Wires...

Free to be forked at any time: https://github.com/garrettsworkshop/Warp-SE I’ll put our usual license in later (which is some poorly written document which I have no idea if it’s enforceable) but basically you can do any commercial stuff with it as long as you remove the Garrett’s Workshop...

Someone should redo the WarpSE’s layout for the Plus. Basically just the shape of the board needs changed. A few CPLD firmware changes are required too but nothing major. I can do that part. It can go in the Classic too. All of our products are totally open-source, even for commercial use. We...

I think I just finished the sound fix! It's a bit heavy-handed but it should work well. Every time the sound buffer is written to, the system slows down a bunch for the next 30-40 microseconds. This prevents the Mac from writing sound samples into the buffer too quickly and overwriting the data...

It’s not so much extracting the core but rearchitecting it so it’s quite difficult compared to reading out a ROM. Anyway the AppleSqueezer uses the Spartan-6 which is a good FPGA and it used to be cheap but it has been in short supply lately and its future is uncertain. So I’m gonna use the...

I was really impressed with the Suska 68K10 core. There are a few other cores out there but they were all a bit obtuse and not so well tested. The Suska guy has been making 68k FPGA cores since 2000. He had an earlier core called the Suska 68K00 which started development in 2000 and was stable...

My future to-do list has a few experiments: Posted write buffer--how much does it improve performance? I have written a lot about the two word posted write buffer. This subsystem is part of the connection between the accelerated CPU and the PDS bus. The posted write buffer can store up to two...

There is also a bit more graphics performance to be squeezed out of the WarpSE. Due to a logic mistake, writes to video memory were taking five clock cycles instead of four. Fixing this amounts to a 1% speedup in graphically heavy workloads. Yeah, I think one step at a time. Eventually we will...

Another interesting detail of the WarpSE is how it handles RAM refresh. As we all know, dynamic RAM must be refreshed and during the refresh, the CPU can't access the RAM, potentially slowing down the system. The WarpSE has an interesting way to mitigate performance loss due to refresh. The RAM...

A little more on my development setup. I built this bus probe gizmo to let me directly connect the PDS bus to my logic analyzer. It has a female PDS slot on top so it can accept the WarpSE: Along with a clip on top of the WarpSE's MC68HC000, this lets me probe basically all of the interesting...

Bringup complete. :) Speedometer 3 results at 25 MHz are looking great: 4.1x faster in "CPU" and 3.5x faster in graphics! I thought it would only be up to 3.8x faster. Huh. Here's a video of the unaccelerated Mac SE doing the Speedometer 3 graphics benchmark: And with the WarpSE: Sorry...

Atmel's ATF16V8 GAL substitute is fairly plentiful. I see a total 13,000 units of ATF16V8BQL-15PU in stock at Mouser and Microchip Direct. So looked at replacing the 74xx control logic with a GAL or two. Unfortunately I could only replace 8 74xx gate and flipflop chips using two GALs. So maybe...

Yeah, I would have just done the design but it's not clear to me what kinds of FPGAs will actually be cheap and available in the future. Pre-2020 I'd have used the Altera Max II EPM240. The cost was under $3 each and it would have worked well for this. Now Lattice and Xilinx are both quoting...

Oh, regarding 16 MB, it's fairly different between the IIgs and this card, which is basically an AE RAMFactor clone. IIgs can't use all 16 MB because it has I/O in bank E0/E1 and ROM in banks F0-FF. So you can only use banks 00-DF for RAM, totaling 14 MB. You could sprinkle RAM in the unused...