Following the SkyWater 130nm, Google has recently announced the open-sourcing of the PDK for SkyWater 90nm process and GlobalFoundries 180nm process.
PDKs (process development kits) encompass all the information needed to successfully design a chip for a given process - design rules for transistors and metal interconnects, "standard cells" (pre-optimized structures that implement basic digital functions), etc. Normally, PDKs are only available after the signing of fairly strict NDAs and can only be used with some expensive, proprietary tools. With the open-sourced PDKs, anyone can try their hands at designing a new chip (you still need some skills and quite a bit of money if you can't get Google to pay for you), and there's a preliminary open-source toolchain as well.
Of course those processes are not quite state-of-the art; for rough comparison, the processes now available are broadly similar to those used for PowerPC G4 (or Athlon [64] on the PC side), though probably with different trade-offs (less power, less speed? 90nm is fully-depleted SOI rather than the partially-depleted SOI IBM or AMD were using back then). But you can probably do some really nice stuff already.
Idly wondering how much effort it would be to do a full-custom NuBus chip (NuBusASIC ?
) The issue is likely to be high-speed connections (PHYs) to useful stuff like clocks and DDR, and complex IPs like PLLs (for clock generation internally) - all those are built-in when using FPGAs. And I'm not sure the standard IO cells' drivers would be OK for NuBus, either. At least the processes have 5V I/Os, unlike most current programmable chips, so it should be doable without too many external chips...
PDKs (process development kits) encompass all the information needed to successfully design a chip for a given process - design rules for transistors and metal interconnects, "standard cells" (pre-optimized structures that implement basic digital functions), etc. Normally, PDKs are only available after the signing of fairly strict NDAs and can only be used with some expensive, proprietary tools. With the open-sourced PDKs, anyone can try their hands at designing a new chip (you still need some skills and quite a bit of money if you can't get Google to pay for you), and there's a preliminary open-source toolchain as well.
Of course those processes are not quite state-of-the art; for rough comparison, the processes now available are broadly similar to those used for PowerPC G4 (or Athlon [64] on the PC side), though probably with different trade-offs (less power, less speed? 90nm is fully-depleted SOI rather than the partially-depleted SOI IBM or AMD were using back then). But you can probably do some really nice stuff already.
Idly wondering how much effort it would be to do a full-custom NuBus chip (NuBusASIC ?
) The issue is likely to be high-speed connections (PHYs) to useful stuff like clocks and DDR, and complex IPs like PLLs (for clock generation internally) - all those are built-in when using FPGAs. And I'm not sure the standard IO cells' drivers would be OK for NuBus, either. At least the processes have 5V I/Os, unlike most current programmable chips, so it should be doable without too many external chips...