SE/30 FPU Upgrade

[YMK]

I swapped my SE/30's FPU for a 40MHz part, then fed it a 31.33MHz clock, tapped from the glue chip.

The first step was removing the 16MHz FPU:



Pin 11 on the FPU is the clock input. I bent it outward so it doesn't contact the pad:



Pin 11 on the FPU is connected to the 31.33MHz clock at pin 17 of the glue chip. The wire passes through a via next to pin 17:



Results from MacBench 3.0 and Speedometer 4.0.2:



A bit underwhelming considering clock speed is doubled, but it's an improvement. A 40 MHz oscillator would push it further and still be within spec.

MacBench floating point: +14%
Speedometer FFT: +11%
Speedometer KWhet: +16%
Speedometer matrix: +20%
Speedometer average: +25%

 

[croissantking]

Interesting, could this be pulled off with the CPU?

 

[YMK]

Interesting, could this be pulled off with the CPU?

I haven't tried this since none of my SE/30s have socketed CPUs, but I think so.

The GLUE chip uses only /DSACK termination, not /STERM.

PDS cards that use /STERM may break.

 

[croissantking]

That would be an easy way to get a 2x speed boost. Seems a bit too good to be true because if you look at any of the 030 upgrades that fit in the CPU socket, they have a very large amount of logic.

 

[YMK]

Seems a bit too good to be true because if you look at any of the 030 upgrades that fit in the CPU socket, they have a very large amount of logic.

That logic is typically for the L2 cache, which is optional.

 

[croissantking]

Pff, don’t need L2 cache. It makes barely any difference on my IIci.

So I’m going to have to try this.

Would it be as simple as desoldering the CLK pin of the 68030 and running a patch wire to the output pin of Y2? Or better to connect to the C32M output of UH7?

 

[croissantking]

I tried this and it 100% does not work. Just seeing a simasimac.

The 25MHz chip in there should be good for 31MHz.

Any ideas?

 

[YMK]

C32M passes through R28 (47 Ohms). You could try tapping the clock on the other side of that resistor.

Also, I'd tape the wire down against the board. Otherwise it becomes an antenna.

Does the C16M signal work?

 

[croissantking]

C32M passes through R28 (47 Ohms). You could try tapping the clock on the other side of that resistor

No-go on that.

Does the C16M signal work?

It does, if I feed the bodge wire to the PDS slot C16M it starts.

I found some info about this Sonnet card that clock doubles the SE/30 on Everymac.com. Looks like they have some logic to get things working. Would love to get my hands on one to reverse engineer.

 

[YMK]

No-go on that.

Did you see any bus activity with C32M?

I found some info about this Sonnet card that clock doubles the SE/30 on Everymac.com. Looks like they have some logic to get things working. Would love to get my hands on one to reverse engineer.

First thing I'd check is whether that 030 is getting a steady 32MHz clock or if it varies.

A steady clock would break burst transfers for PDS cards so /CBREQ and /CBACK on the accelerator might be floating.

My guess is the GLUE is holding the /DSACK lines too long for the 32MHz 030 and part of accelerator's logic involves re-framing those signals, along with /STERM for PDS cards.

 

[croissantking]

Did you see any bus activity with C32M?

I don’t yet have a logic analyser - sorry.

This has been discussed before, I just found: https://68kmla.org/bb/index.php?threads/se-30-overclock-is-it-possible.5186/post-58845

 

[croissantking]

Also,

Mac68k Forums: SE30 Overclocking ...

 

[YMK]

Gorgonops noted the same thing about the /DSACK lines:

I've not done more than skim the 68030 reference manual and while section 7.2.8 covering asynchronous bus operation does say is supports being used in that manner there still seem to be areas that would be affected by the timing relationship between the two being "completely random". (For instance, time window limitations on when and how long the DSACK* lines can be asserted, etc. There's also some verbage in the in-depth descriptions for the asynchronous read/write cycles that further make me wonder what havoc might be wreaked if the clocks were to end up badly out of phase.)

There wouldn't be phase drift problems with C32M since it's locked to C16M, but the ack signals from GLUE would have to be cleaned up by accelerator logic.

 

[croissantking]

would have to be cleaned up by accelerator logic.

If you think you might be up to the task of designing such a circuit I’d be interested in working with you on it.

 

[YMK]

If you think you might be up to the task of designing such a circuit I’d be interested in working with you on it.

That would be a fun project, however I'm tied up at least for the next few months.

 

[croissantking]

Pff, don’t need L2 cache. It makes barely any difference on my IIci.

I may need to take this comment back. Reading into it a bit, the cache is quite important as it would alleviate the wait states imposed by running the CPU asynchronously. I actually have a feeling that an accelerator like Sonnet Allegro SE/30 would provide only a minimal improvement in performance.

 

[Bolle]

My guess is the GLUE is holding the /DSACK lines too long

This.
Those clock doublers for 030 machines massage /DSACK, /STERM and /CBACK to get things working. You'll also need software patches to get sound and floppy working again because those rely on specific timing variables.

First thing I'd check is whether that 030 is getting a steady 32MHz clock or if it varies.

Can't speak for the Sonnet upgrade, but on the clock Doubler made by Dove it runs on a steady 32MHz clock.

 

[YMK]

I may need to take this comment back. Reading into it a bit, the cache is quite important as it would alleviate the wait states imposed by running the CPU asynchronously. I actually have a feeling that an accelerator like Sonnet Allegro SE/30 would provide only a minimal improvement in performance.

Looks like Byrd has one: https://68kmla.org/bb/index.php?threads/sonnet-doubler-allegro-se-30-accelerator-pics.39398/
Maybe he has benchmarks.

This.
Those clock doublers for 030 machines massage /DSACK, /STERM and /CBACK to get things working. You'll also need software patches to get sound and floppy working again because those rely on specific timing variables.

Good to know. I knew there were audio issues with accelerators on the SE, but doesn't the ASC manage the sample clock on the SE/30?

 

[croissantking]

Looks like Byrd has one: https://68kmla.org/bb/index.php?threads/sonnet-doubler-allegro-se-30-accelerator-pics.39398/
Maybe he has benchmarks.

Reading through a bit, they had issues with instability and then discovered that the CPU was only rated to 16MHz. Definitely an accelerator built on the cheap. Still fascinating though.