SE/30 Reloaded graphics issue - anyone else seen this?

[croissantking]

I've been posting extensively over on 68kmla.org but I wanted to ask here as well, since I know there are a quite a lot of compact Mac enthusiasts who don't frequent the other forum.

I've been working to resolve an issue with my SE/30 Reloaded builds and it's become something of a serious endeavour. The issues manifest as graphical anomalies, typically on a cold boot after around 6-8 minutes, peaking in intensity, then clearing up around the 20 minute mark.

One of two types of visual disturbance appears depending on which version of the PAL chips are inserted at UE6 and UE7. Apple put out two versions over the lifetime of the SE/30.

It's not bad chips or a soldering issue – I have meticulously assembled three PCBs from JLCPCB doing exactly the same thing. I've checked all the new parts to make sure they're in spec. And I've spoken to at least a couple of other users with the same issue but between us, so far, we haven't found a solution.

Has anyone else seen it? Photos below.

I've also uploaded videos to Youtube. On both, skip to around the 9 minute mark:

 

[YMK]

The type 1 artifacts I would guess are related to the VRAM address muxes.

The corruption is confined to the display rows which are being written at the time.

The timing on the input select lines of 74F253 (UA8, UB8, UC8, UD8) pins 2 and 14 may be marginal due to signal reflections.

You could try a 110-220 Ohm resistor between each of the A/B select lines and ground (2 resistors total).

 

[robin-fo]

My Reloaded board has similar issues, also appearing and disappearing in a similar fashion as with your board.
The „funny“ thing about these distortions is that they are preserved when you do a cmd+shift+3 screenshot


Thread 'SE/30 Screen Artefacts'
https://68kmla.org/bb/index.php?threads/se-30-screen-artefacts.41023/

 

[croissantking]

My Reloaded board has similar issues, also appearing and disappearing in a similar fashion as with your board.
The „funny“ thing about these distortions is that they are preserved when you do a cmd+shift+3 screenshot


Thread 'SE/30 Screen Artefacts'
https://68kmla.org/bb/index.php?threads/se-30-screen-artefacts.41023/

Interesting - it's similar to my type 2 issue with dashes that build up in columns, but yours are squares and your columns are closer together. I can screenshot those too, but not the type 1 issue with horizontal tearing.

Which version of PAL chips do you have at UE6 and UE7?

Did you come up with any theories as to what's causing your issues?

I tried 100ns, 120ns and 150ns VRAM BTW, they all do the same thing, so it's not because of that.

 

[croissantking]

Solved!

Macintosh SE/30 logicboard recreation (thread revival)

I'm a little unclear on exactly how to implement the fix. The photo above of the factory bodge wire shows it going from (a test point apparently connected to) pin 14 of UG7 to under the socket on UI6. Where does it go? And would that bodge be applicable to the Reloaded board? This is how I've...

68kmla.org

 

[YMK]

Solved!

Nice work!

The short version, from what I gathered:

• The enable input (pin 6) on UE7 in the original design was tied to /NUBUS.
• /NUBUS is generated by the GLUE and mirrors /AS, but is limited to a range of addresses.
• /NUBUS also lags behind /AS enough to cause intermittent display artifacts.
• The address filtering on the /NUBUS signal is redundant since that's also done by UJ6 via the SLTE-F line.
• The bodge involves switching UE7 pin 6 from /NUBUS to /AS.

The schematic redraw at https://github.com/mishimasensei/macse30mlb shows the original design. Hopefully @Elemenoh or Quorten can fix it.

 

[Elemenoh]

@YMK is this fix only applicable to the reloaded board or are you saying that fix is the bodge seen on earlier rev original boards?

 

[YMK]

@YMK is this fix only applicable to the reloaded board or are you saying that fix is the bodge seen on earlier rev original boards?

I believe it's the bodge on earlier Apple boards.

On my 0820-0260-A board, there's continuity between UE7 pin 6 and /AS at the PDS connector (C9).

 

[Elemenoh]

Before this get's merged, it'd be good to have a few people sign off that it looks right. Pages 1,3,5,6 and 8 were updated. Page 5 shows UE7 Pin 6 going to AS* and the other sheets update their AS* reference to include page 5. The edits were in a newer version of KiCAD that messed up text alignment and lost track of a couple of symbols. Those things were fixed, but call out if you see any similar issues.

 

[croissantking]

Before this get's merged, it'd be good to have a few people sign off that it looks right. Pages 1,3,5,6 and 8 were updated. Page 5 shows UE7 Pin 6 going to AS* and the other sheets update their AS* reference to include page 5. The edits were in a newer version of KiCAD that messed up text alignment and lost track of a couple of symbols. Those things were fixed, but call out if you see any similar issues.

In your revised schematics, and on Rev04 of the Reloaded board, UE7 pin 6 goes to AS* (UI6 pin 19, UI8 pin 47, UJ11 pin 27, RP7 pin 1).

On an Apple board, UE7 pin 6 goes to LAS* (UI6 pin 3, UK8 pin J2, RP8 pin 15, PDS pin 89).

I don't understand the discrepancy.

 

[YMK]

On an Apple board, UE7 pin 6 goes to LAS* (UI6 pin 3, UK8 pin J2, RP8 pin 15, PDS pin 89).

I've confirmed continuity between those four points on an Apple board.

Earlier I used the PDS pin label /AS, but the schematic label is LAS*. My apologies if this was misleading.

 

[Elemenoh]

I deleted the revised file from my post to avoid something misleading out there.

Perhaps it'd make sense for someone to create a fork and revise to show the bodge, while leaving the original redraw as-is.

 

[croissantking]

I've confirmed continuity between those four points on an Apple board.

Earlier I used the PDS pin label /AS, but the schematic label is LAS*. My apologies if this was misleading.

Everyone’s been talking about /AS. I think it’s the same signal as /LAS but generated independently. Like one is a repeat of the other. I don’t really understand why you’d have that, but I have confirmed an SE/30 board works fine either way (with UE7 pin 6 going to either /LAS or /AS).

 

[YMK]

Everyone’s been talking about /AS. I think it’s the same signal as /LAS but generated independently. I don’t really understand why you’d have that, but I have confirmed an SE/30 board works fine either way.

UI6 may be filtering LAS* for the SWIM/UJ11 based on the FCx lines.

GLUE/UI8 has its own FCx connections so I'm not sure why it would use *AS rather than *LAS.

*LAS would have the lowest latency for UE7 since it goes right to the 030.