Noticed this unpopulated header while playing with the logic board on my G3, here's a picture with it highlighted from wikimedia:
My guess is an unpopulated mezzanine slot or similar, but does anyone have any actionable info? Could be fun to hook something up to it...
What version of Open Firmware does your iMac have? Output from
dump-device-tree might be useful.
https://forums.macrumors.com/thread...l-work-in-a-beige-power-macintosh-g3.2303689/
Looking at Open Firmware 4.1.9f1 (for a slot loading iMac G3), it looks like it will probe device numbers 0xB to 0x1F (usual IDSEL range) for pci0, pci1, and pci2 PCI host controllers. I haven't researched how interrupts are assigned or how many interrupts there are to assign in this case.
For an mlb-bridge (whatever that is), it will probe device numbers 0x0 to 0xF. I don't think iMac G3 has a mlb-bridge, but this limit exists in all PowerPC Macs for PCI devices behind any PCI bridge. That's a problem for some bridges that might have slots for device numbers in the 0x10 to 0x1F range, like in my Netstor NA255A PCIe expansion chassis. In that case, a nvramrc patch is required to force probing all slots.
So where in the device tree will your two new PCI slots exists? You have IDSEL at PCIAD_18 and PCIAD_19 so I guess they'll have device numbers 0x12 and 0x13. pci0 has AGP. pci1 has Mac-io and two USB controllers. pci2 only has ethernet, so I would guess that's where the two slots will be hosted?
Looking at the
built-in-names properties:
pci0:
@B: UNI-N
@10: AGP
pci1:
@12:Firewire
@13:Ethernet
@17:MAC-IO
@18:USB0
@19:USB1
pci2:
@E:FireWire
@F:Ethernet
I don't see pci1/@12 and pci1/@13 devices in the device tree dump that I have. Maybe this is where your new PCI slots will connect? 5 devices on a single bus seems like a lot.
I also don't see pci2/@E in the device tree dump that I have.
I wonder if it is necessary for IDSEL ranges to not overlap between the 3 PCI host controllers? Or maybe it's cosmetic.
PCI slots have four interrupt pins. Your breakout only has one per slot. How are they wired on the PCI slot? How are they wired on the interrupt controller side?