Bank Distinction on PMX500 and 7200 DIMM?

[trag]

So I understand that 72 pin SIMMs use the /RAS signals to distinguish between and separately activate different banks.

How is this done on the 168 pin FPM DIMM? There's a Bank signal, B0 on the DIMM, but the 9500 HDN claims this is tied to A0. The 9500 lists four /RAS lines, suggesting two per Bank, grouped how?

But the PM 7200, which can use the same DIMMs, only claims two RAS lines in its HDN. Perhaps the Hardware Developer Note is wrong? On the other hand, the PM 7200 HDN doesn't say anything about B0 being tied to A0. But if they can both use the same DIMMs, the Bank scheme can't be different...?

Anyway, anyone know? I can always tone out a 128 MB DIMM and see what it does, but figured someone might already know.

I'm still fascinated by the suggestion that the 7200 might support 256 MB DIMMs.

The 9500 says it supports 16M X 4 parts, suggesting that it can support a bank size of 128MB, but the note specifically says the maximum bank size is 64 MB. There seem to be a number of little inconsistencies like this in the Hardware Developer Notes wrt RAM.

 

[joevt]

Hardware developer notes at:
https://leopard-adc.pepas.com/documentation/Hardware/hardware2.html#//apple_ref/doc/uid/TP40000979
Schematics here:
https://www.macdat.net/repair/apple_schematics.html
I guess they are not enough to answer your question?

For the 7200 using Platinum memory controller, it looks like 8 RAS lines, 2 per DIMM slot, 4 DIMM slots. Each RAS is used twice per slot, 4 RAS pins per DIMM slot.

For the 9500, using the Hammerhead memory controller, there's 13 RAS lines from the memory controller, 12 for the DIMM slots. These go through some kind of transformation on sheet 5. So the signals become 12 odd and 12 even pairs.

7200:

    8 of these from Platinum - 2 per DIMM - 1 per DIMM side - 4 DIMMs with 2 sides each - 64 bit datapath.
    DRAS(0) +-> J17 pin 30
            \-> J17 pin 45
    DRAS(1) +-> J17 pin 114 ; reserved in the developer note?
            \-> J17 pin 129 ; reserved in the developer note?

9500:

    12 of these from Hammerhead - 1 per 2 DIMM sides - 12 DIMMs with 2 sides each - 128 bit datapath.
    HHRAS(1) +-> BUFRAS_O(1) +-> RAS_O1(1) -> B1 pin 30
             |               \-> RAS_O2(1) -> B1 pin 45
             \-> BUFRAS_E(1) +-> RAS_E1(1) -> A1 pin 30
                             \-> RAS_E2(1) -> A1 pin 45
    HHRAS(2) +-> BUFRAS_O(2) +-> RAS_O1(2) -> B1 pin 114
             |               \-> RAS_O2(2) -> B1 pin 129
             \-> BUFRAS_E(2) +-> RAS_E1(2) -> A1 pin 114
                             \-> RAS_E2(2) -> A1 pin 129

Schematics show that A(0) and B(0) are related for both the 7200 and 9500 (though the 9500 has the B(0) signal buffered)

7200 developer note says:

The smallest bank size supported by the Platinum IC is 4 MB and the largest is 128 MB; the largest DIMM supported is a two-bank DIMM holding 256 MB.

I don't know about this. I tried installing 256 MB DIMMs in the DingusPPC pm7200 emulation. The ROM HwInit will not detect 256 MB DIMMs (or 128 MB banks). If 128 MB banks can work in real hardware, you would need to modify the ROM to detect the RAM. I suppose you could try making a nvramrc script to make the changes to the Open Firmware device tree and the Platinum memory controller registers. If you did make such a modified ROM, then I might as well modify that for DingusPPC to add 256 MB bank support to allow 2 GiB of RAM. I think all other machines emulated by DingusPPC don't have memory controller registers that allow 2 GiB of RAM (well, Grackle might have an extra bit to use). That probably doesn't matter as long these memory registers aren't used later by the OS - therefore, any machine can have 2 GiB if the environment is setup properly before the OS starts.

 

[joevt]

A 128 MB DIMM is represented by two 64 MB banks in the Hammerhead and Platinum memory registers.
In DingusPPC, 64 MB DIMMs and smaller are represented by a single bank but I suppose they could be represented by two banks also (i.e. two 32 MB banks for a 64 MB DIMM).

The 7200 developer note suggests that you could have a 128 MB bank; i.e. a 128 MB DIMM would not necessarily be represented by two 64 MB banks in the Platinum memory controller registers.

 

[joevt]

On the DingusPPC Discord, you can find some memory controller documentation.
Search for these:
filename:Platinum_ERS_1.0.pdf
filename:Hammerhead_ERS_Rev_1.1_19950925.pdf

 

[trag]

The schematics show the wiring, but not the behavior. I've also crawled through the Hammerhead ERS document and it does not shed light either. I suspect the necessary information might be in the JEDEC standards for the supported DIMMs.

Thank you for the suggestions though.

Are you able to please provide a link to the Platinum ERS document?

Just to make things more interesting the 7200 HDN also mentions in a rather offhand way that the 7200 supports up to 1 GB of RAM.

 

[joevt]

Here's the Platinum ERS.

 

[trag]

Just started reading, but the Platinum ERS document states right up front that it supports up to eight, 128 MB banks of RAM on four DIMMs.

 

[trag]

Looking through the Hammerhead and Platinum documents carefully, they strongly suggest that banks are controlled on a /RAS basis, however, Hammerhead is weird. Each pair of DIMM sockets gets the same two /RAS lines. This makes perfect sense, I think, when the machine is operating in interleaved mode, at least for reads. And I guess for writes it would work, as long as one always sent 128 bits at a time and sent the proper data to each DIMM....

But I don't see how this could work at all when the sockets are not interleaved. Perhaps strategic use of the /CAS lines.

Buffers on the /RAS signals are probably for signal strength. Hammerhead only sends out a single /RAS signal which is meant to activate two separate banks on different DIMMs, which might have 16 chips on each DIMM. Thirty-two chips is a lot of load for one signal out of Hammerhead.

Also, Hammerhead does support a Bank signal B0, but why? I guess that may require looking carefully at the schematics.

One final, irrelevant note is the interesting fact that Hammerhead actually has a 13 /RAS line for motherboard DRAM. Never implemented by Apple, although Umax did include motherboard DRAM on the S900/J700. I wonder if they used that special /RAS line, or one of the lines for unused DIMM sockets (S900/J700 has 8 sockets, not 12).

 

[joevt]

Just started reading, but the Platinum ERS document states right up front that it supports up to eight, 128 MB banks of RAM on four DIMMs.

Maybe the hardware allows it. I don't think the ROM HWInit memory detection routines for Platinum might not.

I've attached startup trace from DingusPPC. Ignore the sound DMA which is happening in another thread to play the boot chime while the RAM is being checked (the boot chime is played by a DBDMA program in the guest machine).

FFF04524 - It sets the 8 BANK BASE registers to 128 MB each starting from the last one. All 1 GiB should be addressable at this time.

FFF0454C - Then it checks each bank to see what size it is.

FFF04140 - It writes a value KurtLiza to the last 8 bytes of the 64 MiB range.
FFF041C0 - It reads 8 bytes from each MiB starting from the first MiB until it sees the value that was written.
FFF041DC - The size is detected at this point.
FFF03628 - It writes the calculated base (0 for the first bank) to nvram 1048 and size (64 MB) to nvram 104C. The second bank is stored in the next nvram addresses and so on.

This algorithm is used for banks ≥ 64 MB or when writing to the end of the 64MiB range is mirrored for smaller banks. i.e. A bank that is only 8 MiB would be mirrored 8 times inside the 64 MiB range and the algorithm would find the bytes at the end of the first 8 MiB.

If this does not hold true for the bank, then an alternate algorithm starting at FFF0419C is used to find the bank size. DingusPPC does not emulate the mirroring of smaller banks so this alternate algorithm always happens for banks ≤ 32 MiB.

So you see that it doesn't try to detect if 128 MiB banks exist.

Looking through the Hammerhead and Platinum documents carefully, they strongly suggest that banks are controlled on a /RAS basis, however, Hammerhead is weird. Each pair of DIMM sockets gets the same two /RAS lines. This makes perfect sense, I think, when the machine is operating in interleaved mode, at least for reads. And I guess for writes it would work, as long as one always sent 128 bits at a time and sent the proper data to each DIMM....

But I don't see how this could work at all when the sockets are not interleaved. Perhaps strategic use of the /CAS lines.

Also, Hammerhead does support a Bank signal B0, but why? I guess that may require looking carefully at the schematics.

I'm not going to try to understand RAS/CAS bank select etc.

One final, irrelevant note is the interesting fact that Hammerhead actually has a 13 /RAS line for motherboard DRAM. Never implemented by Apple, although Umax did include motherboard DRAM on the S900/J700. I wonder if they used that special /RAS line, or one of the lines for unused DIMM sockets (S900/J700 has 8 sockets, not 12).

DingusPPC lets you use this motherboard RAM to achieve 1.625 GiB of RAM on machines that use Hammerhead.

Attached TNT ERS. No Catalyst ERS.

 

[trag]

So you see that it doesn't try to detect if 128 MiB banks exist.

I wonder if this is an artifact of using the same ROM on both the PowerSurge and Catalyst machines. PowerSurge doesn't support greater than 64 MB per bank (although the HDN details suggest otherwise) and no noe could build such a DIMM back then, so why bother to write in support for greater than 64MB on Platinum?

Pure speculation on my part, but I could see that being the case.

If I ever get far enough along, it won't stop me from actually trying it in hardware, though...

 

[joevt]

I wonder if this is an artifact of using the same ROM on both the PowerSurge and Catalyst machines. PowerSurge doesn't support greater than 64 MB per bank (although the HDN details suggest otherwise) and no noe could build such a DIMM back then, so why bother to write in support for greater than 64MB on Platinum?

The algorithm for Hammerhead is different than for Platinum.

Platinum Bank Base registers support addresses with this mask: 0x7FE00000 - 2 MiB resolution < 2 GIB.
Hammerhead base address registers support addresses with this mask: 0x7FC00000 - 4 MiB resolution < 2 GiB.

The algorithm for detecting Platinum bank sizes begins by setting each of the 8 banks to different 128 MiB boundaries but it won't detect 128 MiB banks so it's limited to 512 MiB total.

The algorithm for detecting Hammerhead bank sizes begins by setting each of the 26 banks to different 64 MiB boundaries. It will detect 64 MiB banks but not 128 MiB banks so it's limited to 1664 MiB. The last step of the algorithm interleaves pairs of banks that can be interleaved.

In either case, some Open Firmware code could maybe alter the memory controller registers to allow for up to 2 GiB of RAM but only if the hardware is capable. In DingusPPC, there is no hardware so it's probably capable.