Bank Distinction on PMX500 and 7200 DIMM?

[trag]

So I understand that 72 pin SIMMs use the /RAS signals to distinguish between and separately activate different banks.

How is this done on the 168 pin FPM DIMM? There's a Bank signal, B0 on the DIMM, but the 9500 HDN claims this is tied to A0. The 9500 lists four /RAS lines, suggesting two per Bank, grouped how?

But the PM 7200, which can use the same DIMMs, only claims two RAS lines in its HDN. Perhaps the Hardware Developer Note is wrong? On the other hand, the PM 7200 HDN doesn't say anything about B0 being tied to A0. But if they can both use the same DIMMs, the Bank scheme can't be different...?

Anyway, anyone know? I can always tone out a 128 MB DIMM and see what it does, but figured someone might already know.

I'm still fascinated by the suggestion that the 7200 might support 256 MB DIMMs.

The 9500 says it supports 16M X 4 parts, suggesting that it can support a bank size of 128MB, but the note specifically says the maximum bank size is 64 MB. There seem to be a number of little inconsistencies like this in the Hardware Developer Notes wrt RAM.

 

[joevt]

Hardware developer notes at:
https://leopard-adc.pepas.com/documentation/Hardware/hardware2.html#//apple_ref/doc/uid/TP40000979
Schematics here:
https://www.macdat.net/repair/apple_schematics.html
I guess they are not enough to answer your question?

For the 7200 using Platinum memory controller, it looks like 8 RAS lines, 2 per DIMM slot, 4 DIMM slots. Each RAS is used twice per slot, 4 RAS pins per DIMM slot.

For the 9500, using the Hammerhead memory controller, there's 13 RAS lines from the memory controller, 12 for the DIMM slots. These go through some kind of transformation on sheet 5. So the signals become 12 odd and 12 even pairs.

7200:

    8 of these from Platinum - 2 per DIMM - 1 per DIMM side - 4 DIMMs with 2 sides each - 64 bit datapath.
    DRAS(0) +-> J17 pin 30
            \-> J17 pin 45
    DRAS(1) +-> J17 pin 114 ; reserved in the developer note?
            \-> J17 pin 129 ; reserved in the developer note?

9500:

    12 of these from Hammerhead - 1 per 2 DIMM sides - 12 DIMMs with 2 sides each - 128 bit datapath.
    HHRAS(1) +-> BUFRAS_O(1) +-> RAS_O1(1) -> B1 pin 30
             |               \-> RAS_O2(1) -> B1 pin 45
             \-> BUFRAS_E(1) +-> RAS_E1(1) -> A1 pin 30
                             \-> RAS_E2(1) -> A1 pin 45
    HHRAS(2) +-> BUFRAS_O(2) +-> RAS_O1(2) -> B1 pin 114
             |               \-> RAS_O2(2) -> B1 pin 129
             \-> BUFRAS_E(2) +-> RAS_E1(2) -> A1 pin 114
                             \-> RAS_E2(2) -> A1 pin 129

Schematics show that A(0) and B(0) are related for both the 7200 and 9500 (though the 9500 has the B(0) signal buffered)

7200 developer note says:

The smallest bank size supported by the Platinum IC is 4 MB and the largest is 128 MB; the largest DIMM supported is a two-bank DIMM holding 256 MB.

I don't know about this. I tried installing 256 MB DIMMs in the DingusPPC pm7200 emulation. The ROM HwInit will not detect 256 MB DIMMs (or 128 MB banks). If 128 MB banks can work in real hardware, you would need to modify the ROM to detect the RAM. I suppose you could try making a nvramrc script to make the changes to the Open Firmware device tree and the Platinum memory controller registers. If you did make such a modified ROM, then I might as well modify that for DingusPPC to add 256 MB bank support to allow 2 GiB of RAM. I think all other machines emulated by DingusPPC don't have memory controller registers that allow 2 GiB of RAM (well, Grackle might have an extra bit to use). That probably doesn't matter as long these memory registers aren't used later by the OS - therefore, any machine can have 2 GiB if the environment is setup properly before the OS starts.

 

[joevt]

A 128 MB DIMM is represented by two 64 MB banks in the Hammerhead and Platinum memory registers.
In DingusPPC, 64 MB DIMMs and smaller are represented by a single bank but I suppose they could be represented by two banks also (i.e. two 32 MB banks for a 64 MB DIMM).

The 7200 developer note suggests that you could have a 128 MB bank; i.e. a 128 MB DIMM would not necessarily be represented by two 64 MB banks in the Platinum memory controller registers.