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Yeah, you can put a double riser card in that accommodates an accelerator and an Ethernet/video card. It’s tight but it can be done

Nooo!! A 30-pin SIMM is too narrow in terms of data bus width. It's got eight 1-bit chips so altogether you only get 8 bits, but the IIsi needs 32 bits of RAM data. You can grab the chips off a 72-pin SIMM and that will work.

I mean, it’s open source so you can do anything with it you want. We’re going to be selling 25 MHz units, but I am just seeing how much further it can go. There are always the “worst case” and “typical” specs in engineering specifications including for chips. So if I bump the clock up too far...

Just grabbed the Sony-Tektronix AWG2040 out of storage. I’m gonna use it to try overclocking the WarpSE. This thing can output an arbitrary waveform at up to 1 gigapoint per second: This piece of equipment is admittedly overkill for clock generation purposes. It can output any wave and at quite...

Yeah. Now if someone could come up with the Verilog code or logic schematic of a SWIM chip, we could just integrate that on the WarpSE and put our own 20-pin floppy connectors. Big Mess O' Wires has his Yellowstone disk controller for the Apple II but I think it's only an IWM, not a SWIM. I'm...

Now the real question is, why hasn't someone reimplemented the SWIM? It's just a state machine... Someone oughta do that. I'm only good at processors and RAM controllers. I kinda suck at I/O so someone else oughta tackle that project.

No! I just wanna be clear that this isn’t true. The SWIM isn't something you can flash or store somewhere to enable 1.44M floppy support. The WarpSE will have the FDHD ROM but not the SWIM chip. It's not something that can be added to the Mac without connecting to the floppy drive. So you will...

I'm convinced doing this is the key to becoming a good engineer. Back in 2015/2016 I was working on this Bluetooth audio gizmo for Hondas and Acuras. We wanted to sell it but the margins on the product were going to be very tight and we had to make a large initial batch of these things...

Nah, let’s just eliminate the dip switch altogether. Why not? Then people will feel like they have to read the manual instead of just install it and go. I can’t see the need for any options except in one specific case. If the computer crashes during a flash, you need to use the “motherboard ROM”...

Well actually I’m gonna eliminate 20 MHz mode because it’s not that useful. Why not just go 25 MHz? That’s 25% better lol. And motherboard ROM mode is going away as well since it’s also not too useful except for fixing a bad fast ROM flash. You can just use the update system to fix that instead...

Prototypes are currently being made :) Some board mods are needed. Our only working board looks like this: Not too pretty. Our prototypes should be a bit cleaner.

On that note, should we sell an FDHD ROM kit for the SE? Obviously due to the WarpSE’s fast ROM it’s not necessary with the accelerator. The specific pinout of the SE FDHD ROM is not compatible with flash or EPROMs so you have to have a custom board. We sell our Apple IIgs ROM01 replacement...

They've got the Apple Sound Chip (ASC) which fixes a lot of the limitations of the SE sound. See here: https://se30forever.com/sound.html That link goes over the basics but the original designer has a bit more to say about the timing here...

Oh and on the subject of testing @JDW @alxlab @Kai Robinson I have had you guys in mind as beta testers so let me know if you have a working SE to try the WarpSE in and I'll send you one.

New idea for the sound fix. If I can get this to work before I send out test units that'll be great. The sound slowdown works well now but it's not cycle-accurate. That would be more robust but the current hardware can't pause the fast 68k's clock. I thought this would make cycle-accurate sound...

Well I just shortened the refresh from taking four cycles to taking three cycles. In this arrangement, the RAM is slightly "overclocked." So I can't ship it but it gives an idea of the impact of hiding that one additional refresh cycle. With this, the latency of a refresh coinciding with ROM...

I guess we should always refresh after the first clock of an I/O read since they always take a long time to complete. But again that doesn't help graphics since QuickDraw never accesses the I/O devices. Maybe there's enough room in the CPLD to "save up" some refreshes with a counter. Then when...

Yes yes this is basically it. I guess this is called “global scoreboarding” in the context of CPU branch prediction. It almost works but it needs another idea before it’ll improve performance. The issue is that we need more than one speculative refresh strategy. Then we can choose which to apply...

Just finished what I hoped would be the last bit of performance tuning on the WarpSE relating to RAM refresh but there is one remaining issue. I currently have the speculative refresh feature implemented like this: This RS0toRef variable gives the conditions under which a refresh is executed...

@JDW I have a question... have you ever used Big Mess O' Wires's ROMinator flash utility? It looks like this: What if you have to use a similar utility to reflash the WarpSE's fast ROM? It'll take a minute or two to flash so it's slower than a control panel settings but you shouldn't need to...