(2) Macintosh SE/30's - Full Restoration

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caver01

Tinkerer
Oct 30, 2021
207
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Glad to know D(31) can go missing and still POST correctly, thanks for the input. What caused your D(31) to break in the first place? Was it battery or cap related?

SO, I think the generalization gets mistakenly applied because address and data lines are on a “bus” and many components are tapping into that bus in parallel. I am perhaps oversimplifying it, but in my case, D31 may have only been broken between CPU and SCSI (or more likely, it was D31 on SCSI alone—I don’t recall). What I DO know is that it failed continuity between the SCSI chip and the CPU. Given the routes of these bus traces, it might be that it was a trace near the SCSI chip that corroded due to cap electrolyte and D31 would tested clean between the CPU and other components! Now that would really have been frustrating if I had been trying to move forward under an assumption that D31 in general was ”GOOD”.

In any case, it was the SCSI symptom that led to my checking continuity between the address and data lines, and that’s how I found it. Once I bodged what was a known failed connection, electrically, the bus was repaired again having bridged the broken location. To date, I don’t actually know where it failed. Maybe a via? I probably fixed other components relying on it at the same time.
 

caver01

Tinkerer
Oct 30, 2021
207
145
43
I could ask the question: what Address lines could be broken to cause a simasimac condition - and never get an answer

To my point, I think the question is too broad— you would need to ask, what Address lines could be broken between chip X and chip Y, or from the bus to chip X and so on. A broken address line to the sound chip, for example, might be fine until audio kicks in. That was the case while troubleshooting the ACS for example—the OS would freeze if you played any audio. At POST, it would appear to work, but no chime.

Yet, the same address line broken at the ROM could present as simasimac. I think it just depends where and what.
 

caver01

Tinkerer
Oct 30, 2021
207
145
43
Thinking about this a little more— given the inevitable electrolyte leaks happen across all of the boards in roughly similar locations, we have good techniques to find the common issues, but now that I am long past the point of frustration or impatience, I find that the variances from case to case, and the potential random impacts are what makes each of these “fun” and unique! Even the veteran experts here haven’t seen everything, and there are likely still surprises to discover by the next troubleshooter. The community definitely helps!
 

patters

Tinkerer
Feb 3, 2025
54
46
18
I have purchased a few things from overseas since the tariffs began, none of them were $3 with $60 shipping.

EDIT: 30% was the steepest charge for shipping plus the tariff fee on ebay, on my past purchases.
It's the same nonsense in the other direction for us Europeans. USPS rates quoted by most suppliers are similar, and yet we can have stuff air freighted from China for a tenth of the cost.
 

GreenBar0n

Tinkerer
Dec 22, 2025
71
36
18
East Bay Area, CA
To my point, I think the question is too broad— you would need to ask, what Address lines could be broken between chip X and chip Y, or from the bus to chip X and so on. A broken address line to the sound chip, for example, might be fine until audio kicks in. That was the case while troubleshooting the ACS for example—the OS would freeze if you played any audio. At POST, it would appear to work, but no chime.

Yet, the same address line broken at the ROM could present as simasimac. I think it just depends where and what.

From the Simasima Repair Guide:

1. After initial power-on, and the voltages stabilize, the sound chip releases the reset line
2. The CPU begins executing code
3. The GLUE logic maps the ROM to the start of the address space (address $0)
4. The CPU begins executing code from the ROM SIMM using one of the VIA chips
5. Boot-time diagnostics check if the system is operating normally. If any failures are detected or the user presses the NMI
(non-maskable interrupt) button:
A. A "Sad Mac” tone is played (if the sound chip and circuitry is working and it is able to be selected by the GLUE logic).
B. The system ROM will attempt to start Apple Test Mode.
This mode will attempt to set up communication with the SCC (serial port controller) and Apple’s TechStep hardware
diagnostic tool. Note, this can be simulated with a serial connection.
6. After all tests pass, the ROM will remap the RAM into address $0 (by use of the VIA) and the system ROM will attempt to
initialize video memory by with the video ROM.
7. The remainder of the boot process commences


I've noticed if at least (4) good RAM SIMM's are not installed, simasimac occurs, but a bad Address line in the RAM banks still seems to allow Apple Test Mode to operate and produce a Sad Mac. If you can move the (4) good RAM modules to either Bank 0, or 1, which may not contain the bad Address line, you can still get to a Sad Mac and then be able to connect to the logic board with a serial cable, or TechStep and locate the bad Address line.

A broken Data line seems more likely to prevent the Apple Test Mode from starting at all - and without Test Mode operating it's much harder to diagnose.

The Address lines broken to the Glue chip at A(0) and A(1), or to the VIA chips from the CPU, could be a likely problem too.
 
Last edited:

Mark_W

New Tinkerer
Feb 2, 2026
3
3
3
I opened my se30 again tonight as I noticed some of the smd 74hc logic ic legs are still a bit tarnished and reflowed all of them. While I'm at it I did more tests and found some interesting results.

If I remove ROM stick and let it boot to horizontal bars, all frequencies on address lines are halved, exactly the same as your measurements. I can only get ~2.6Mhz on A2 when ROM is installed:

2654.jpg


2656.jpg


Maybe our boards are different from the reference one used in the guide? My board's behavior is exactly like your first one.

Also I tried to block several address/data lines on the ROM stick by covering them up with kapton tape. Tried several different ones and they all result in horizontal bar. Well that's somewhat expected once I think about it since cpu can't read and execute the ROM, it can't initialize the vram and it will get stuck at horizontal bar.

However, how the system will behave if address/data lines from the cpu to the rest of the chips are severed is still unknown. Probably unstable system or non-working peripherals.

Anyway, what we do know for now is that some boards have different address line frequencies when ROM stick is removed, maybe we can suggest an edit to the repair guide. Also, never skip checking continuity from PDS slot to cpu lol.
 
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GreenBar0n

Tinkerer
Dec 22, 2025
71
36
18
East Bay Area, CA
Regarding only getting 1.305MHz at A(2) Pin 4 - when the ROM is removed: I think the Simasima Repair Guide was stating what the Frequency Target should be for each Address line with the ROM inserted, or as as a perfectly functioning Logic Board; yet when running the CPU/Walk the Bus Test, they say to remove the ROM, and I think they just forgot to mention what the Frequency Target should be without the ROM.

I have (2) SE/30 boards that behave that same way, and I asked ZigZagJoe on 68KMLA and he confirmed that without the ROM there is no 2.62MHz at A(2). That would make (4) SE/30 Logic Boards that have confirmed without the ROM inserted, 1.305MHz is what you get for A(2). It was very confusing to me being a new user of the Guide, I thought I had an issue with my clocks as a result of that mismatch.
 
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Mark_W

New Tinkerer
Feb 2, 2026
3
3
3
I took another look at the repair guide:

With the ROM removed, the CPU will walk the bus from A(2)
through A(31). On a working board, A(2) at ROM pin 4 will display
a ~2.6 MHz square wave. Each address following should be half
the frequency of the bit that precedes it. A(3) is ~1.3 MHz, A(4) is
~655 kHz and so on.

And on page 46 the scope shows square wave with 50% duty cycle, and its measurement is indeed 2.6MHz (pg 46):
1770168923720.png


If ROM is installed, A2 will not show a perfect 50% duty cycle square wave, instead some irregular waveform as data is flowing on the bus (pg 88):
1770169215936.png

Frequency of the square wave is 1/(2.5*400ns)=1MHz. This waveform matches perfectly with my measurement, which frequency is 1/(5*200ns)=1MHz.

So I think the guide isn't necessarily wrong, there might be a different motherboard revision that gives different frequencies. My friend also has an SE30 in perfect condition (no battery leakage or capacitor leakage damage) which I recapped last year. iirc it's an early revision with socketed 68030, I will borrow it from him and run some more tests.