I'm almost done with the final WarpSE board and overclocking board! All of the issues and weaknesses I could identify have been fixed, and there are some new features on the WarpSE since the last version:
As I said before, the
SiTime MEMS oscillator is as accurate as a crystal, but has better temperature stability and can handle higher peak G-forces which would shatter the crystal in a crystal oscillator.
In this version, the WarpSE can
OR the power from USB and the Mac so that it can be programmed outside of the Mac. Since the CPLD can now be powered up with the Mac off, recent firmware versions since 0.6b have had a power fail detector that automatically tristates (disables) the signals going from the WarpSE's CPLD to the Mac's PDS bus when the Mac is off. The power fail detector works by measuring the frequency and duty cycle of the Mac's 7.8336 MHz "C8M" clock relative to the onboard 25+ MHz oscillator. If the C8M clock is not toggling, the Mac's power must be off or browning out, so in this case, the WarpSE disables its outputs onto the PDS.
Associated with the USB power input is a new
fuse and inrush current limiter. The purpose of the fuse is obvious enough, but the inrush current limiter is interesting and less obvious. Per the USB specification, a device may not have more than 10 µF of capacitance directly on the +5V power line of a USB device. If there's more capacitance, when plugging in the device, the inrush current could large enough to brown out the PC’s USB power. The WarpSE has over 100 µF of capacitance on its +5V rail, so that’s not good to plug directly into USB. In order to have more than 10 µF of capacitance, you have to apply an inrush current limit circuit between your big capacitance and the USB power. The inrush current limiter ensures that the capacitance is charged up slowly to avoid browning anything out. So this has been added to the USB power input of the WarpSE.
The
address bus remapping capabilities have been improved, although the full address remapping capability will not be enabled on production boards. This new board has the ability to do any remapping on the top four address bits going from the fast bus to the PDS. This would let us remap any address $YXXXXX to $ZXXXXX. However, on production boards, remapping for address bits A23, A21, and A20 will be disabled, and only A22 can be remapped. This is to save space in the CPLD, since one logic element in the CPLD is required to implement each address bit that's remapped. Recent versions of the WarpSE firmware have been using 125-139 of the 144 logic elements, so I don't feel comfortable spending an additional 3 logic elements for this function that might not be useful. We might need that extra space in the CPLD to fix a bug later. Just being able to remap A22 lets the WarpSE access 2496 kB of extra motherboard RAM (if you have 4 MB installed). It's not contiguous, but it will be useful as a ~2.5 MB RAM disk.
The "
bleeder resistors" are probably not necessary, so I may not actually place them. They're just to help the WarpSE more quickly discharge its power capacitance when powered off. Disadvantage is they waste power while the system is on.
And finally there's the
overclocking connector. It of course is for use with the little overclocking board which I described before:
I changed the 32 MHz setting to 33 MHz to even out the frequency spacing. I'm excited to try this overclocking board since I never got around to hooking my fast waveform generator up to the WarpSE and overclocking it that way.
Just bought all the parts for 50 overclocking boards from JLCPCB! Once they're in I'm gonna have the boards assembled by JLC. WarpSEs themselves will of course be made under my and Garrett's supervision in our little semi-automated factory.
One other change in the main WarpSE board is to how the ROM banking works. The total flash ROM size in the WarpSE is 1 MB. The top two bits of the ROM address bus come from the CPLD, so the ROM can be banked in certain ways. I plan to store the Mac Classic ROM (512 kB), Mac SE ROM (256 kB) and Mac SE FDHD ROM (256 kB) in the ROMs on the final WarpSE. Only one of these ROMs will be enabled at a time, selectable via firmware update. The USB update system is really slow so the key here is that all three ROMs are always in the onboard flash, and updating the ROM just changes the CPLD a little to select a different ROM. The FDHD ROM will be default but the non-FDHD SE ROM is also present in case there's a problem on systems without a SWIM. The Classic ROM works on the SE and it has the benefits of the ROM disk, but it's of course experimental on the SE.
So in order to select one of the 256 kB ROMs (original SE or FDHD), the CPLD sets the top two address bits going to the ROM. In the case of the 512 kB Classic ROM, the CPLD must set the top address bit but then pass the lower bit through from the address bus. The current WarpSE can do this but the two ROM bank bits are multiplexed with the RAM address bus. This works fine but it means that the CPLD has to react to whether an access is to RAM or ROM and send the right data on the lines that are shared between RAM addressing and ROM banking. That takes extra time and I neglected to include that delay in the CPLD in my overclocking wait state analysis. The extra delay in the CPLD might mean that even at 30 MHz, a ROM wait state is required for reliable operation. Therefore in the latest revision, the ROM bank bus has been separated from the RAM address bus. The ROM bank bus still comes out of the CPLD, but when using a 256 kB ROM like the original SE or FDHD ROM, the bits are set statically and never change, so the timing is not affected. This is as opposed to currently, where the CPLD would have to see the ROM address range and then drive the static bank for the current ROM. Unfortunately still when running a 512 kB ROM the CPLD has to buffer the lower bank bit, reintroducing the delay. So when running the Classic ROM, a ROM wait state may be required at all frequency settings, even 30 MHz. No big deal though.
Soon I'll get this board revision fabbed and the WarpSE will be on its way to release!