A WarpSE/30 accelerator with two PDS connectors and a 24-bit video card with VGA and HDMI for the SE/30 PDS would be fantastic! Is that on your following project list
@Zane Kaminski?
Long answer if I am to be thorough but I guess I'll write a bunch about a possible “WarpSE/30" since I've been asked so many times in varying levels of detail. A really great accelerator for an '030 system is a difficult project to truly get right. I had the WarpLC partially done six months ago but abandoned the design:
This was gonna go in the LC, LC II, CC, etc. and add a 33 MHz ‘030, FPU, 64 MB SDRAM with 32-bit width and 4-1-1-1 timing (75 MB/sec), 32 kB L2 cache (inside the FPGA), and ESP32 for WiFi networking. It has since been canceled! I will explain the various reasons why but let me first say a few things we believe in doing differently with our accelerators:
Onboard RAM
Firstly, we believe in maxing out the system RAM with RAM onboard the accelerator. The 4 MB of RAM on the WarpSE is cheap and its inclusion obviates the need for L2 cache which would just be a few kilobytes. The onboard RAM is fast enough to keep pace with the 25 MHz 68k so no faster cache is needed. On SE/30 the benefits of maxing out the RAM on the accelerator are more pronounced. The obvious thing is price. 128 MB in 30-pin SIMM format is expensive. We used to have the best price at $80 but the SIMM market too cutthroat so we had to quit. The same 128 MB in SDR SDRAM just requires four chips costing $1-2 each. And with onboard SDRAM, we can design a really fast RAM controller capable of more bandwidth than any 68k Mac, including the IIfx and Quadra 840AV. So we are committed to always maxing out the RAM no matter what.
Minimizing legacy parts
Second, we are highly disinclined toward using legacy chips. The WarpSE misses the mark here. Most of the WarpSE’s chips are new but the RAM and 68k CPU are legacy. These chips are not made anymore and their prices will rise and quality will decline (by that I mean that there will be counterfeits, used chips with bent pins, etc.) over time. Old chips use a lot of power and space on the board and their presence also prevents us from meeting the latest environmental standards. The current WarpSE design is already fast so I would say that the primary goal for the
next generation of WarpSE is to eliminate the legacy RAM and CPU. Well, we could hook modern SDRAM up to the current WarpSE easily enough but replacing the CPU will require an FPGA, and one with about 100x more logic resources than the little Xilinx CPLD serving as the the WarpSE’s chipset. We could keep the old 68k in the next WarpSE revision but I feel strongly that we must at least adopt SDRAM. SDRAM is 3V-only and the 5V-amplitude signals put out by an old MC68HC000 will blow up an SDRAM chip if connected directly. So to add SDRAM, we would have to put more of those pesky little buffer chips in between the RAM and 68k:
The function of the buffer chips is to safely take in the 5V-amplitude signals from the 68k and output 3V signals which are safe for the SDRAM. Only a few tens of cents each but they are a bit of a pain. If we instead put the 68k in an FPGA, we can actually eliminate some of the buffers instead of having to add more because of the SDRAM. Fortunately Melkhior has pointed out the open-source Suska 68K10 core. Looks to be a well-tested, 25 MHz-capable 68000 implementation which we can use for the future WarpSE. Unfortunately there are no suitable open-source 68030-compatible CPU cores so any ‘030-based accelerators (such as for LC or SE/30) will have either make due with a “real” 68030 for now or uhh, not exist.
No passthrough connectors
Third, we are highly disinclined toward PDS pass-through connectors. It sounds good but you get into a 3V/5V level-shifting problem sorta similar to what I just described. I’ll elaborate. For the WarpSE, it was acceptable to use a small, simple FPGA (referred to as a “CPLD”) to implement the accelerator “chipset.” The function of the chipset is to control the onboard RAM, transfer data between the accelerated CPU and main motherboard, etc. This older CPLD can interface directly with the Mac’s 5V signals, saving us from having to add more of those little buffers. But for an ’030 accelerator, even if we are using a separate CPU outside of the FPGA, there are too many things the chipset has to do: burst transfers, 16/32 bit byte steering, L2 cache, etc. An old, small, 5V-tolerant CPLD won’t cut it. So we need to use a new, 3V-only FPGA. That means more of those little buffers to translate between 5V and 3V. The 5V/3V bus distinction makes it difficult to route the pass-through on the board too. Look at the back of the DiiMO030 accelerator with pass-through:
On the DiiMO030, it seems that the the signals from the bottom PDS connector go straight up to the passthrough connector on top, hitting any chips they need to connect to on their way through the middle of the board. On a possible WarpSE/30, since the 5V PDS signals can’t directly connect to the FPGA and SDRAM, none of the PDS bus passthrough wires go to anything but the two connectors and the buffers at the bottom of the accelerator card. Routing those signals through the middle of the board would make a big mess of the layout since they don’t have anything in the middle to connect to. So to simplify routing and minimize required layer count in the board, the whole PDS bus has to sort of go around everything to reach the passthrough on top. See this layout concept which convinced us not to do the passthrough:
Not too much room for the go-around! Notice how on the now-abandoned WarpLC design, we avoided this pesky detail. Basically the same architecture but no passthrough so the layout is nicer:
Much simpler layout without the passthrough! The final strike is the matter of the PDS connector itself. The 96-pin EuroDIN connectors like on the SE and LC PDS can be obtained cheaply from Chinese manufacturers. But few Chinese manufacturers make the SE/30 PDS’s 120-pin connector and it’s quite a bit more expensive from the well-known American/European manufacturers. Last I checked it was like $7 for the 120-pin SE/30 PDS connector from Molex versus $1-2 for the 96-pin SE/LC/Portable/NuBus connector from a no-name Chinese factory. Chinese connectors are good! I like the cheap plastic used in cheap connectors. Doesn't melt as easily as the softer plastic from the fancy connector companies. And then there’s the matter of soldering the connector pins! We have mostly automated surface-mount production using our pick-and-place machine and conveyor reflow oven. We like doing the production ourselves. Saves money and we get to be in charge of the quality. But we have to hand-solder through-hole stuff like the PDS connectors. Obviously we have to put on at least one PDS connector in order to have an accelerator, but we would rather not solder the additional 120 pins for the passthrough. It would be easier to put more surface-mount chips to implement the video card or whatever. So overall it’s just a big headache in every way for the passthrough and we should be building new network and video implementations anyway rather than supporting the passthrough. Also the PDS passthrough is necessarily 15.6672 MHz, whereas if we built the video card directly onto the accelerator's fast bus, updating the screen would be way faster.
Okay now back to the WarpLC and WarpSE/30. We wanted to make the WarpLC and then enhance that architecture into the WarpSE/30. The LC is less powerful than the SE/30 so 33 MHz would be acceptable for an LC accelerator but an SE/30 accelerator oughta be 40 or 50 MHz. Plus the SE/30 accelerator has to have the full 128 MB RAM instead of 64 MB on the WarpLC. LC owners don’t expect a passthrough since the computer has onboard (low-res) video output and nobody is expecting to add a network card and an accelerator. So the plan was to ship the WarpLC as an accelerator with WiFi hardware but no driver support, then work on the WiFi driver, and then once it was done, do the WarpSE/30 with integrated networking and possibly video. (And of course the WarpSE/30 would have no passthrough.)
So why did we cancel the WarpLC and therefore also the WarpSE/30?
Well, the most immediate reason was that we based this design fairly heavily around the Xilinx Spartan-6 FPGA, which since the beginning of 2022 has been unobtainable and is slated for discontinuation by Xilinx. We were planning on using some specific Spartan-6 features which are not present in other vendors’ FPGAs. We didn’t anticipate the Spartan-6 discontinuation in September 2021 when we started the WarpLC design. Second, these designs have like 21 of those little buffers. That’s a lot! They’re cheap enough ($0.15 nominally, $0.25-0.35 these days) but 21 is a ton of those little things.
Third, the WiFi interface on the WarpLC is supposed to be a clone of my NuBus WiFi card concept which has been languishing. The NuBus WiFi card hardware is in need of a redesign. I think it would be prudent to work on that first before dreaming up
another, separate product that’s supposed to integrate the unfinished networking.
Fourth and probably most importantly,, maybe we should be focusing on the problem of implementing the 68030 rather than implementing the supporting logic of the rest of the accelerator. I looked just now on eBay at 68030 prices. For a 40 or 50 MHz chip, it’s at least $35. Many of the chips are fake too, as reported by many of our members and others. When I say “fake,” I don’t really mean that the chip doesn’t work or isn’t a 68030, but that it has been “refurbished” and re-marked with a faster speed grade and newer mask revision. Makes it difficult to 40/50 MHz if we have to bin the chips ourselves. And then what do we do with the slow chips? Return? The sellers will take them back, but if you return too much stuff on eBay at once, you start getting emails about eBay’s “abusive buyer policy.” Hahah, what about an abusive seller policy lol… We are anticipating the counterfeit chip problem getting worse as opposed to better. Once we have our 68030 core in hand, this whole problem will be solved and everything will get faster and cheaper. With everything internal to the FPGA, we will be able to reduce RAM and L2 cache latencies, increasing performance. There will be fewer buffer chips, since we don’t have a 5V 68k CPU which must be connected to the 3V-only FPGA and SDRAM. And of course we won’t have to spend $50 on the 68030 and 68882.
Regarding what you said about shying away from doing a lot in an FPGA, I can see how an FPGA 68030 might not feel like a win from the perspective of a vintage chip purist. I do understand. Garrett and I are obsessed with a few Honda/Acura models. Our favorites are the 2004-2008 “CL9” Honda Accord / Acura TSX and the 1996-2000 “EJ” Honda Civic. We own both. Garrett owns the Civic and Garrett’s Workshop owns the Acura TSX (it used to be mine), both with manual transmission of course. We have other (newer) daily drivers but we never wanna give up the TSX and Civic. What we like about the cars is this sort of beautiful unity between the driving feel, the engineering prowess, and the overall cost of ownership. Very much like the Mac. Fun to drive but then you start fixing the car and you see the sublime engineering. So minimal but so robust and good and reliable and smart. I love Honda and I love Apple for basically the same reasons. But eventually our Civic and TSX will be unmaintainable. Come 2025, Honda will no longer be legally obligated to produce parts for the Civic. Aftermarket parts are almost all garbage, except the fancy racing ones which are usually a lot more expensive than the parts from the dealer. In the Civic, all the rubber suspension bushings were totally shot after 20 years and we replaced them with polyurethane ones from a well-respected racing parts brand. Polyurethane lasts much longer than rubber but it gives a distinctly harsher road feel. I think we would have preferred new original rubber bushings. The Acura is worse lol, it’s been crashed into on the side. Had the body pulled to spec but it has some lingering suspension problem we’ve been too busy to figure out. We want a new 2008 Acura TSX and a new 2000 Honda Civic! And we don’t care if the cars are in an FPGA! Hahahah…
My point with the Honda-Apple comparison is that old parts are going away and will be steadily rising in price. Where do you get a 2008 Acura TSX A-Spec 6-speed manual with tech package that’s not trashed? Very hard to find, and nobody is making new 2008 Acuras. Fortunately we can sort of do this with Apple stuff. But just like the cars, we have not forgotten the importance of the original feel! With everything we do, we aim for complete compatibility, reliability, and above all, to preserve the original Macintosh feel! Over in the Amiga community, Gunnar van Boehm has his (closed-source) “Apollo 68080” core which he claims is 20x faster than a 68040. That’s all well and good but we would not want to put too fast of a CPU in our accelerator. One of the signature elements of the classic Mac is how it sort of takes a moment to redraw stuff when you move a window around. We don’t wanna make that imperceptibly fast, just less annoying than the old slow speed. The feel is important.
So, to answer your question in the most succinct way, yes, we are working toward the WarpSE/30 but there is a good bit of important work to be done first. Even if we settle for a physical 68030+68882 instead of the FPGA 68030, we should at least get the NuBus WiFi card done so as to be able to integrate it. The FPGA market is also pretty unstable now and it would be best to wait for it to stabilize before designing the WarpLC again around another FPGA just for it to be discontinued again because of the chip shortage.
Long message! Hope it clarifies something about our thinking.
