WarpSE: 25 MHz 68HC000-based accelerator for Mac SE

Lovemyclassicmacs

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Mar 31, 2022
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Hi all,
Just wondering once the card is complete with the 000 cpu in place. If you decided to add a 030 chip for instance what are the limitations to doing it?
 

Ubik

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Nov 2, 2021
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I've found that in upgrading the SE with a 16mhz 68000 SpeedCard , a good thing about using a faster 68000 vs 030 is better stability and compatibility. It seems much less crash and fuss than my 020 Radius 25 or my Mobius 030. Also the SE's 16 bit data path tends to hamper the advantage of the 020 or 030.
Someday when we can get new SE/30 logic boards, then the 030 will shine in the SE . . . but I guess it won't be an SE :)
 

Zane Kaminski

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Hi all,
Just wondering once the card is complete with the 000 cpu in place. If you decided to add a 030 chip for instance what are the limitations to doing it?
It wouldn't be that hard to swap it out in the layout but the current design is pretty strictly 68HC000-focused. There are a number of things I'd do differently were I using an '030. Maybe in the future!




Okay the current hang-up is just on the logo. Still not sure what to go with. Garrett and I both really like @alxlab's design but it doesn't exactly fit with the font and stuff we've chosen for the website and text on the products. I just haven't given this much thought. Will revisit this soon.
 
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Trash80toG4

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Regarding your logo conundrum: I like that version as well, however "reverse italics" imply sloooooow speeds and have never been offered in .txt formatting AFAIK?

Italics imply fast speeds, that this is based purely upon vertical slit oriented focal plane shutter photographic effect may or may not enter into your decision process. But I'd steer clear of anything with even a passing resemblance to round wheels screeching to a halt in a cartoon for an accelerator logo. :p

edit: that should be vertical travel of horizontally oriented focal plane shutter slit.
 
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JDW

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...the current hang-up is just on the logo. Still not sure what to go with. Garrett and I both really like @alxlab's design but it doesn't exactly fit with the font and stuff we've chosen for the website and text on the products. I just haven't given this much thought. Will revisit this soon.
"Great artists steal" — i.e., concoct your own design with inspiration from existing designs.

Consider these examples.
 
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Zane Kaminski

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"Great artists steal"
But also, "real artists ship!" So we have reverted to the old temporary logotype:
FrontIsom.png

The prototypes are in fabrication!
 

JDW

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Yowza, Zane!
25MHz 68000 with full compatibility with older software (whatever runs on a normal SE), plus the ability to use a Fast ROM too, all in a super compact size.

Without going through all the previous posts, what is the estimated ballpark price?
 

Zane Kaminski

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Yowza, Zane!
25MHz 68000 with full compatibility with older software (whatever runs on a normal SE), plus the ability to use a Fast ROM too, all in a super compact size.

Without going through all the previous posts, what is the estimated ballpark price?
I’m confident we can do the first 100 production units for $125 each but after that there may be a price increase to $150ish.
Edit: Oh, also there will be a surcharge of approximately $15 for shipping outside of the United States. Shipping anywhere in the US is free.

This is really exciting! This might be the first Mac SE accelerator I might actually be able to get
:) You’re on our short list of beta testers. And @JDW too
 
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JDW

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Q: What is the "sound QoS" or "sound rate limiter?"
A: It's a fix for a behavior in the sound driver in the Mac ROM that causes audio glitches when running with an accelerated processor. .... The fix for this is to slow the CPU way down when accessing the sound buffer.
@Kay K.M.Mods and several other people who have installed Bolle's clone of the Carrera040 have discovered that there are audio glitches on the SE/30, but apparently not on other Macs like the IIci, when the 040 on the accelerator is being used. I guess it must be a similar problem to what you described. So if the solution for your forthcoming card is to "slow down the CPU when accessing the sound buffer," that might be what's needed to fix the Carrera040. Kind of off-topic, I know, but on-topic as far as your description is concerned.

— — —

QUESTION: Why allow switching between 20MHz and 25MHz? Why not just make it a fixed 25MHz? There obviously must be a reason for the 20MHz setting, right?

— — —
You need the SWIM floppy chip (as opposed to IWM) on your SE motherboard in order to use 1.44 MB disks.
I had the understanding that in addition to the SWIM chip, you must also have the newer 342-0701, HI ROM & 342-0702, LO ROM too, otherwise, with the new SWIM chip and the older 342-0352-A, HI ROM & 342-0353-A, LO ROM, you only get 800K floppy compatibility, even with a 1.44MB floppy drive mechanism.
 

Zane Kaminski

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@Kay K.M.Mods and several other people who have installed Bolle's clone of the Carrera040 have discovered that there are audio glitches on the SE/30, but apparently not on other Macs like the IIci, when the 040 on the accelerator is being used. I guess it must be a similar problem to what you described.
Could be. I can investigate in the future if we do an SE/30 accelerator.

QUESTION: Why allow switching between 20MHz and 25MHz? Why not just make it a fixed 25MHz? There obviously must be a reason for the 20MHz setting, right?
Yes, the reason is that the 68HC000 was only ever officially specified for 20 MHz operation. 25 MHz is technically "overclocked." However it is widely understood that nearly all 'HC000s (especially later mask revisions) are capable of 30 MHz and faster speeds. I am sure that all WarpSE units will work at 25 MHz but if you are not so confident, you can reduce the speed to 20 MHz using the DIP switch. Interestingly, the WarpSE chipset doesn't support arbitrarily low clock speeds for the accelerated processor. 20 MHz is near the minimum. If you decrease the clock speed below something like 18 or 19 MHz (can't remember the exact figure), there will be a certain race condition and the bus bridge between the fast and slow buses will exhibit random failures. So you can't run at 16 MHz, for example. Around 20 MHz is the practical minimum.

I had the understanding that in addition to the SWIM chip, you must also have the newer 342-0701, HI ROM & 342-0702, LO ROM too, otherwise, with the new SWIM chip and the older 342-0352-A, HI ROM & 342-0353-A, LO ROM, you only get 800K floppy compatibility, even with a 1.44MB floppy drive mechanism.
Yes but we are reproducing the "FDHD" ROM in the "fast ROM" flash chips on the WarpSE, so all you need is the SWIM chip and FDHD drive. @alxlab has verified that the newer ROM works even with an older IWM chip or an 800k drive. Of course if you switch the DIP switch to the "motherboard ROM" position, you will be using whatever ROM is in your Mac SE's motherboard, in which case you need to have the FDHD ROM on your SE's motherboard in order to use 1.44M disks. The "motherboard ROM" setting is mainly for if you manage to corrupt the fast ROM chips as using motherboard ROM severely reduces performance. The fast ROM flash chips are protected from accidental erasure by a coded command sequence that must be input before an erase/write command can be executed, but it is possible to purposely reprogram them using (for example) BMoW's reflash tool for the Mac ROMinator. If something went wrong during the reprogramming process, the WarpSE would be bricked without the motherboard ROM setting. With the setting you can boot up using motherboard ROM and use a utility program to reflash the fast ROM and fix the accelerator.

Oh also @JDW, since you did not read the entire thread, maybe you didn't catch what I consider to be one of the the key feature of the accelerator--the longword posted write buffer. This is a feature of the interface between the 20/25 MHz accelerated CPU bus and the slower 7.8336 MHz bus on the SE's motherboard. Without it, the accelerated CPU would have to slow down to 7.8336 MHz when writing to the screen framebuffer memory. Instead, the posted write buffer allows the fast CPU to "post" two words of data (2 bytes) up to twice in a row with zero wait states (i.e. at full speed). After doing so, the fast CPU can go on executing from fast RAM or ROM while the posted write data is trickled out to the slower 7.8336 MHz bus. And of course all of RAM and ROM are cached on the card, as opposed to other accelerators which cache just a subset of main memory.
 
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Andy

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Oct 31, 2021
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This is such a cool project. My SE and I are looking forward to it as well. It would be cute to make a little badge that fits in the front panel like the old contemporary accelerators did.
 
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