Search results

Got a fabulous breakdown of the entire project to date: DevLog in Claud's color coding for emphasis, not mine. Inquiry: That was a very long session with several unrelated tangents, the first being my failure to make sure you got my diagram of the PDS adapter. Fair point — that imageshack...

continued: The four offset rows of 15 header pins added to the component side of FPD card interface with same rows of sockets on the PDS adapter card. What's the pin /thruhole size for that connector and is it a standard pitch? Read 6 pages, searched the web Yes — 0.1" (2.54mm) is standard...

This session was very long, mostly due to my initial question being too complex. Claude went off on several tangents, some unrelated. I should have asked if he could access the images I’d set up in a new album on ImageShack before posing my list of questions. It would have saved much of his...

Interesting, watching a video about imaging a card I got the impression that running an emulator on a PC was the route I'd need to take? Macpack was a source mentioned, but it looked like I’d need to set up an emulator. I’ve decided that each operating system on its own dedicated SD card is the...

Thanks, I was thinking that would likely be the case. Yeah, I can imagine your SE drags, I don't recall whether I ever took my SE to 7.0.1 or left it at 6.0.8. It had the Radius16 in there so was no slouch working as my plotter server after having been the production machine before the IIx...

Did you get an SE image tuned up? Is there an image available with partitions that'll let me load and choose from four or five systems/OS?

Deserving of much more than a like! Kindred spirits unite! :ROFLMAO:

Should I spin the AI connector search out to a dedicated thread? Seems like a nifty trick, but maybe something obvious, not worth the effort? edit: added the connector search post to a new "Leapfrog" listing in the IP.

edited in missed steps in the above post in blue, interesting stuff I'd think? __________________________________________________________________________________ continue the PCB reverse engineering project Waiting for a few things to arrive to get the SE up and running for card function...

Nice! Congratulations on getting them up and running. Curious about board production, minimum quantities and price point? Haven't seen enough of that kind of thing to make heads or tails out of it. edit: how many layers?

continue the PCB reverse engineering project Buzzed most of U22, the VIAs within its footprint and some long runs toward the top I wanted to get in the works. Interesting mess. Does anything come together at this very early point? A few real threads are already visible, even this early —...

Mini update: - I've annotated the pinouts for every IC with Claude's guidance - Completed the Solder Side tracework - Reoriented the original point of view from PDS on bottom Solder Side to ICs upright either view. - Hairline Solder Side traces ovelay views showing connections/VIAs between...

continue the PCB reverse engineering project New file config check: New AI9 file created for buzzing Component Side connections from Solder Side View, giving access to all signals and the VIAs obscured by ICs topside. - at .036 revision level, component side file is Picture-Layer Locked - at...

Somewhat disjointed session, wound up mixing and matching two AI streams. :rolleyes: ______________________________________________________________________________________________________________________ 260915 Session 2 – pinout check continue the PCB reverse engineering project Finish up...

continue the PCB reverse engineering project Finish up pinout check from last session. Hopefully I got the corrections taken care of. Sourced pinouts for unverified ICs. Lets see if it all comes together in an AI9 file? It's coming together well — one fix confirmed landed, one new thing to...

continue the PCB reverse engineering project FPD-Comp-Pinout-015.ai9 Pinout Verification – FINAL! Am I good to go? - layer visibility check of file? - thinking no template to be seen again in this one? FPD-Comp-Template-015.ai9 - saved with all layers visible - found the “Include Attached...

continue the PCB reverse engineering project Pinout Verification VRAM Pinout Discrepency – real or did I induce it in reformatting your files? AI9 file import test: – layers work? – does the attached template image come thru or do I need to upload it with AI file? The pinout files you’ve...

This one's pretty cool, while Claude was having trouble nailing down a pinout I did an end run and did it visually before he reported back. Great stuff, it's like dueling abilities and dueling limitations all at once.. Sweet music to my eyes! :)...

It's a thing of beauty all right! Still curious about the methods (trials and tribulations) of the LCD image shift.

Thanks, that summary is very much appreciated! Looks great. - I won't be doing the schematic capture, Claude will do that from my Solder and Component side "coloring books." - I imagine the PCB design will be done for me as well. ;) Hoping the long form play by play might have others wondering...