TwiSlot PCI Riser and ComSlot2 NIC repro in widened CS riser form factor

[Trash80toG4]

The schematic for J8 of the 6500 says the reserved pins are for a PCI adapter card. I suppose the PCI adapter card is an Apple specific adapter so it can do weird stuff like requiring reserved pins to handle separate interrupts.

The 6x00 two slot Riser is indeed specific to Alchemy/Gazelle and definitely does weird stuff:

Three Slot Riser for 6400 - In search of the Mythical Slot C

The connector at the bottom has 194 pins, 97 on each side. The pins aren't numbered in silk screen, so for my purposes, I numbered them from left to right on the front. On the back, I did not flip the card over. Pretend you're looking through the board, oriented as above, and the back...

68kmla.org

Apple was involved in the development of NuBus with MIT et al. So of course in implementation they did Apple things to the standard. Each Slot had a unique identifier line outside the NuBus spec. It appears they did the same when implementing PCI in Alchemy, circumventing the decoding of Interrupt combinations in the PCI spec, using Reserved lines for nefarious Appleish purposes. In the New World Beige G3, Apple implemented standard Interrupt decoding, which is why the tentacled three slot RA risers for Rackmount conversion work.

Haven't tested it yet. Snagged it for the card cage to use in my 2UBG3 build. Another one tested out just fine as I figure this one will and bolts up nicely to the card cage if needs be.

Where's the schematic for the riser (PCI adapter card?)? Are you sure its INTC at A7 of slot_B? Is INTA at A6 of slot_B wired to something? I think every slot needs to have all INTA,B,C,D wired to something, otherwise a PCI device that uses one of those interrupt lines won't work.

There is no known schematic of the riser. been developing that on and off for five years now. Slot C quest was a spinoff from the TwinSlot adapter for my 6360 the 5x00 and another form factor adapter for the TAM.

Thanks for the wake up call on the INT lines! Forgot about discovering that all four lines are tied together on the 6x00 riser and wired to a Reserved line way back when. Just buzzed it out again for confirmation. That simplifies my test lashup/procedure for the Mythical Slot C search immensely!


edit: dunno about Bus Mastering, never heard anything about it not working. Info on that should be in the Designing PCI Cards tome.

 

[joevt]

edit: dunno about Bus Mastering, never heard anything about it not working. Info on that should be in the Designing PCI Cards tome.

I believe bus masters use REQ and GNT (check the PCI local bus specification).
What REQ and GNT lines are you planning to use from OHare for Slot_C?
Heathrow for Gossamer appears to have 6 pairs of REQ/GNT lines.

A bus master is one that can read and write to the Mac's RAM using DMA or read and write to other PCI devices.

 

[Trash80toG4]

Took the day off to play with the woodworking tools. Soldering/Hot Air Rework Station is shaping up nicely!

Haven't updated this one to reflect Reserved Pin A11 being wired to all four Interrupt lines yet.

B10 and A19 Reserved Lines are hooked up to Request and Grant as suggested by Daniël over at the MLA.

His first markup of my AI doodle was:

Never did check what ASIC is at U23, but he let me know which was which on those two Reserved Lines. That left only A11 unaccounted for and then I found that in the Gazelle Schematic he had provided.

Many thanks, Daniël! You too @joevt we'll see what happens over my next MON-TUE off, gotta get the fans/filters set up. The hellacious mess I've made needs to be squared away before I can rewire one of my IDC Cable Risers into Slot_B config and then take a shot at Slot_C if and when.

 

[joevt]

Never did check what ASIC is at U23, but he let me know which was which on those two Reserved Lines. That left only A11 unaccounted for and then I found that in the Gazelle Schematic he had provided.

U23 is the chip on Alchemy. You want U20 on Gazelle. Or am I confused about what machine the goal of these threads are for?
We don't have Alchemy schematics.
U20 is used for doing GNT for 4 of the 5 PCI slots/devices from OHare (page 7-B7). U20 is a 74F32 which only has 4 OR gates so it can only do 4 devices.

Gazelle U20 pins:

        REQ     GNT     GNT
page    OHare   OHare   PCI     Device
====================================================
 6-C6    1       2       3      COMM_SLOT
 6-C2    4       5       6      PCI_SLOT
 6-C2   10       9       8      PCI_SLOT2
16-B2   13      12      11      PCI_VIDEO
 3-B4    -       -       -      PSX_PCI (no connection to U20 - direct connect between OHare and PSX)

 

[Trash80toG4]

U23 is the chip on Alchemy. You want U20 on Gazelle. Or am I confused about what machine the goal of these threads are for?

A little history of this insanity:

Riser is same for Alchemy and Gazelle. Nefarious, Appleish Reserved Line perversion of the PCI specification on the undocumented Riser was discovered by myself some five years ago. At the time I was beginning to look into my TwinSlot Riser Project for 6360, 5x00 and later on the TAM. @trag was helping me with understanding PCI and how it might relate to the Request Line Anomaly. He posted this pic of the multipurpose Alchemy Architecture C600 UMAX Riser with Slot_C on board.

At that point I broke the tangent off into the Search for the Mythical Slot C.

Daniël entered the fray over there because he had a Gazelle board with irreperable damage to its graphics chipset. He had the Gazelle schematic and was working out how to rework its PCI implementation into an actual slot.

So he's working his way up to the PCI interconnect on the Logic Board from the schematic.

I've been drilling down to the Logic board from the Alchemy/Gazelle PCI Riser. I have only a bit of deciphering schematics.

This is the most simple representation of the Slot_C experiment:

No time to post it over at the MLA for Daniël to markup. What do you think of it?

 

[joevt]

Riser is same for Alchemy and Gazelle.

Is the riser that is the same for Alchemy and Gazelle a two slot riser or a three slot riser?

That C600 UMAX Riser is not the same as the Apple Alchemy and Gazelle riser as it has a non-PCI connection with many more pins to accomodate the third slot and a comm slot.

Nefarious, Appleish Reserved Line perversion of the PCI specification on the undocumented Riser was discovered by myself some five years ago. At the time I was beginning to look into my TwinSlot Riser Project for 6360, 5x00 and later on the TAM. @trag was helping me with understanding PCI and how it might relate to the Request Line Anomaly. He posted this pic of the multipurpose Alchemy Architecture C600 UMAX Riser with Slot_C on board.

I suppose any riser with more than one slot has to do something weird unless it has a PCI bridge chip or the slot it connects to is not real PCI. In Apple's case, the PCI slot is a real PCI slot (I think it can connect a real PCI card without the riser?) but it uses some reserved pins for per-slot signals.

At that point I broke the tangent off into the Search for the Mythical Slot C.

Daniël entered the fray over there because he had a Gazelle board with irreperable damage to its graphics chipset. He had the Gazelle schematic and was working out how to rework its PCI implementation into an actual slot.

So he's working his way up to the PCI interconnect on the Logic Board from the schematic.

I've been drilling down to the Logic board from the Alchemy/Gazelle PCI Riser. I have only a bit of deciphering schematics.

This is the most simple representation of the Slot_C experiment:

No time to post it over at the MLA for Daniël to markup. What do you think of it?

That 1726160538698-png didn't come through. As for the other image, it's a little busy with too much information. It might be easier to read if you summarize it in text form, like this:

Slot A:
All PCI pins of Slot A come directly from the corresponding pins of the riser slot since the riser slot is a PCI slot.
INTA-INTD are tied together on the motherboard to PCI_SLOT_INT of OHare.
IDSEL is derived on the motherboard using AD(13).
REQ is PCI_SLOT_REQ.
GNT is MOD_SLOT1_GNT.

Slot B:
Most PCI pins of Slot B come directly from the corresponding pins of the riser slot except the following:
INTA-INTD are tied together on the riser to PCI_SLOT2_INT of OHare using A9 reserved pin.
IDSEL is derived on the riser using AD(14).
REQ is PCI_SLOT2_REQ using B14 reserved pin.
GNT is MOD_SLOT2_GNT using A14 reserved pin.

Slot C:
Most PCI pins of Slot B come directly from the corresponding pins of the riser slot except the following:
INTA-INTD are tied together on the riser to PCI_SLOT3_INT of OHare using A11 reserved pin.
IDSEL is derived on the riser using AD(15).
REQ is ???? using B10 reserved pin.
GNT is ???? using A19 reserved pin.

So what is B10 and A19 connected to on the motherboard? Check the GNT/REQ pairs of OHare.
If they are connected to nothing, then what are you going to connect them to?
If they are not connected to anything then maybe the PCI card will still work but not as a bus master.

 

[Androda]

@Androda I figure you know which interrupt is used on CSII? Maybe that can help narrow things down for the Slot_C search?

It looks like you have the 6500 schematic, the comm slot is on the same page as the PCI slot in there.

Comm Slot II cards appear to have one interrupt pin instead of several like PCI slots. And on the 6500 the CS II interrupt goes to pin 64 of the OHARE chip.

 

[Trash80toG4]

Comm Slot II cards appear to have one interrupt pin instead of several like PCI slots. And on the 6500 the CS II interrupt goes to pin 64 of the OHARE chip.

Thanks much. CSII only needs one interrupt signal, which is equivalent to Slot_B on the Apple Riser, where INTA-INTB are tied together and connected to one of the Reserved lines of the PCI spec.

Is OHARE documented somewhere?

 

[Trash80toG4]

So what is B10 and A19 connected to on the motherboard? Check the GNT/REQ pairs of OHare.
If they are connected to nothing, then what are you going to connect them to?
If they are not connected to anything then maybe the PCI card will still work but not as a bus master.

First, thanks much for translating my diagram into TXT. I'm visual to a fault, needing to see the traces to grok circuits and have great difficulty making myself understood in the forums when limited to TXT. Many years ago at the MLA, I posted a diagram and was encouraged to do so as it helped immensely.

The busy diagram in the above a visual map for me in the process of rewiring an IDC ribbon cable based single slot riser.

That one is a mess because I was thinking I'd have to do a lot of mixing and matching. I'll soon start over on a much simplified version:

1 - test riser for Slot_A function baseline. I know they work, just need to make sure the one I modify works.
2 - split out and label lines to be rearranged to prove my understanding of Slot _B works as advertised.
3 - Split out signal lines for the Slot_C search.

Lines will be spliced to male/female breadboard jumper wires as above, no need for breadboard, we're now down to very few wires and one resistor.

 

[Androda]

Is OHARE documented somewhere?

I don't really know, but the chip appears in the 6500 datasheet.

 

[Trash80toG4]

Once @trag confirmed that Apple took the Reserved pin shortcut to decoding Slot_B Interrupt along with, my initial discovery of Request line bodge to Request on Slot_B on the 6x00 Reserved I was off to a good start

I usually study the Block Diagrams:

Gazelle

Alchemy

But that approach didn't matter given the wonkiness of the Riser. So I started digging down to the non-standard PCI implementation of the Riser Slot from Slot_B with Mk.1 eyeball, riser scans and continuity tester in hand.

edit: had posted wrong Block Diagram for Gazelle: fixed!

Haven't heard back from Daniël over at the MLA as to how I've interpreted his markup of an earlier version of the diagram above.

 

[joevt]

Thanks much. CSII only needs one interrupt signal, which is equivalent to Slot_B on the Apple Riser, where INTA-INTB are tied together and connected to one of the Reserved lines of the PCI spec.

Equivalent in this case means that CSII has the same number of interrupt connections to OHare as Slot_B, just like every other PCI device connected to OHare. Equivalent doesn't mean that CSII and Slot_B uses the same interrupt. All PCI devices connected to OHare have a separate interrupt input on OHare.

Is OHARE documented somewhere?

There may be an O'Hare ERS document somewhere. I don't know where. Do you need more info than what's on sheet 7 of the 6500 schematics? Does sheet 7 not account for every pin of OHare?

 

[Trash80toG4]

Equivalent in this case means that CSII has the same number of interrupt connections to OHare as Slot_B, just like every other PCI device connected to OHare. Equivalent doesn't mean that CSII and Slot_B uses the same interrupt. All PCI devices connected to OHare have a separate interrupt input on OHare.

Indeed, I thought that's what I'd said, thanks for the input if it wasn't clearly stated.

There may be an O'Hare ERS document somewhere. I don't know where. Do you need more info than what's on sheet 7 of the 6500 schematics? Does sheet 7 not account for every pin of OHare?

Not working from the 6500 schematic, was curious is all. Chipping away at the Riser and possible provision for Slot_C by drawing parallels from the Slot_B implementation. Daniël gave me some great feedback for what gets hooked up where based on his schematic analysis. The possibilities I need to test have become manageable.

I posted the two block diagrams to illustrate how he came to be working on this problem. The ATI Graphics Controller takes up one of the four PCI connections. He had irreparable damage to that subsystem and was exploring the possibility of hijacking its PCI PseudoSlot assignment to implement an actual PCI Slot for that board. Interesting project!

 

[Trash80toG4]

Much improved CableMonster Riser test rig. Still boots into Slot A1, tested after every single modification.
Next step is to solder all the breadboard jumper wires, Female/Slot, Male/Edgecard as on the bundled Interrupt lines on gray wire.

Need to document the improvements made so far to the dedicated soldering/rework station.

 

[Trash80toG4]

Latest doodling at work.

Not complete, but gives a good idea of testing methodology.

 

[Trash80toG4]

Finally ready to start soldering jumper wires in the AM! Need to doublecheck everything, was pulling my hair out this afternoon.

 

[Trash80toG4]

Mythical no more . . .

. . . after 5 years 1 Month and 22 Days!

Worked on the first try, thanks to one and all!

 

[joevt]

I think interrupts should be working, so you can move the mouse around the display connected to slot C.
Does the Matrox card enable bus master? Does it have 2D or 3D acceleration?
Try a ATA or USB or FireWire or SCSI card? Some of those probably won't work.

 

[Trash80toG4]

All four interrupts are tied together on the motherboard for Slot_A and on my test riser for all three configurations. Sot_B1 is implemented on Apple's 6x00 Riser just as I've implemented. Can't imagine any reason for Slot_C1 to behave any differently than that OEM riser's Slot_B1.

 

[Trash80toG4]

Couldn't resist Slot_E1 kluge:

Started getting flaky results and now none. Must have broken a connection on the CableMonster which is going into retirement.
I think my TwinSlot Riser project has had its schematic adequately confirmed, so I'm back onto that track again.

Curiosity satiated.