So, don't mean to tell you everything is wonk, but I can't quite understand the posts that you're posting when there is no info behind them... Do you think you could explain what you are doing? In a little bit of words? Thanks!
So, don't mean to tell you everything is wonk, but I can't quite understand the posts that you're posting when there is no info behind them... Do you think you could explain what you are doing? In a little bit of words? Thanks!
Prototyping a data input capture board for the four VRAM chips on the FPD/SE in wire wrap. Remapping pixels in Pi Zero 2 W for output to obsolete LCD displays via HDMI->DVI adapter cable. Titans of FPGA have said the project seems 100% viable. Board is a precursor to implementation in FPGA. If that works out, the FPGA will likely swallow the Radius card whole.
Assistance from a master in the black arts of Pi GPIO would be much appreciated.
Wonk is what I do . . .
edit: Radius 16 accelerator seems ripe for cloning in the FPGA at some point as well. Radius 16/FPD/SE = 1987 DTP machine of dreams for 6.0.8-7.x
BigPics will be thumbnailed later. They're easy for showing them to a Computer Science major at work. He's a whiz at Python. Comic book format pf pics and links make playtime for my noggin at work during downtime.
If 1GHz Pi Zero 2 W won't handle remapping in real time with double buffered single frame delay, Compute Module 5 I/O Board in hand for 2.4GHZ injection. 1.5GHz Compute Module 4 and its I/O board currently reside in PowerBook 100 awaiting emulation to catch up with it. So it's available for testing in the FPD/SE rig, but sacrificial Zero seems the thing to do for now.