Radius FPD/SE - Rotation Transform/HDMI Output via FPGA Project Board - CLAUDE SESSIONS

[JDW]

@JDW could you run a synopsis of this particular session for me? Asking for an outline of the unrelated tangents and lessons to be taken from them in this session would be most helpful. I wouldn't even know where to start to get that result.

Here is an AI-generated (Gemini) synopsis/summary of both pages of this thread...

Reverse-Engineering the Radius FPD/SE Card​

To date, this discussion documents the process of cloning a 1986 Radius Full Page Display (FPD) 64/68Hz card for the Macintosh SE. The project aims to map the board's netlist from the J1 video header backward to the logic ICs and develop an FPGA transform to output the portrait-orientation video signal to a modern landscape-oriented display.

Key Points & Practical Lessons (to date)​

AI Auto-Tracing vs. "Wetware" (Human) Tracing

• Key Point: The user attempted to rely on AI-driven color-threshold auto-vectorization (similar to Adobe Streamline) to map the physical PCB traces.
  
  
• Lesson: Automated segmentation struggles with real-world artifacts like silkscreen bleed, shadows, and low substrate contrast. Human intuition manually tracing over an accurately scaled, perspective-corrected bitmap template is vastly superior for capturing true trace geometry.

Vintage Hardware Workflow Bottlenecks

• Key Point: The reverse-engineering layout was being drawn in Adobe Illustrator 8 on vintage 2004/2005-era Apple hardware (a PowerBook and a Mirror Drive Door Power Mac G4) with memory constraints.
  
  
• Lesson: When bridging modern AI processing with vintage computer systems, file formats must be heavily adapted. Large, high-resolution color PDFs caused memory crashes, so the workflow was optimized by exporting 256-level (8-bit) grayscale JPEGs and older EPS vector formats to keep file sizes manageable while retaining essential visual data.

The 4-Layer Board Theory vs. "Free Real Estate"

• Key Point: Observing a trace passing directly between two unpopulated ROM footprints (U25 and U26) led to speculation that the 1986 card might utilize an expensive 4-layer design with buried planes.
  
  
• Lesson: Before assuming exotic manufacturing techniques, consider simple layout convenience; PCB routing software frequently runs standard 2-layer traces straight through unpopulated footprint pads because it functions as empty "free real estate". To definitively verify PCB layer counts without lab equipment, you can file the edge of the board at a shallow 5–10° angle and apply a liquid emulsion to visually expose the copper stackup.

Disorienting Pinouts and Silkscreens

• Key Point: The process encountered tracking errors when matching IC pinouts, such as confusing pin 9 with pin 11 on TTL chips, and struggling to decipher faded silkscreens.
  
  
• Lesson: Mirrored photos and upside-down chips easily disorient visual counting. The fail-safe method for verifying pinouts is to locate fixed VCC (+5V) and GND (0V) pins using a multimeter on a live board, and count outward from those points rather than relying on the physical notch orientation. Furthermore, when interpreting worn silkscreens, careful human observation with contrast-enhanced zooming outpaces AI image recognition.

END OF SYNOPSIS

---

I then asked Gemini what advice it wishes to give you based on its reading of this entire thread, and it had the following to say...


@Trash80toG4 is absolutely making progress, particularly by building a solid mental model of the board's routing logic and correctly deducing that human intuition outpaces AI for deciphering faded silkscreens and ambiguous traces. However, the current visual, vector-based methodology is effectively playing on "hard mode" and creating significant bottlenecks.

To ensure the reverse-engineering effort results in a functional, electrically sound clone or FPGA transform, here is the specific advice he should consider adopting:

• Transition from Vector Graphics to EDA Software
  Drawing PCB traces in Adobe Illustrator is a purely cosmetic exercise. Illustrator has no concept of a "netlist" or Design Rule Checking (DRC). He should transition to an Electronic Design Automation (EDA) suite like KiCad. Modern EDA tools allow you to import a high-resolution photograph of the board as a background layer, scale it perfectly, and place actual component footprints on top. Routing traces in EDA software builds a logical netlist, ensuring that the schematic matches the physical layout and preventing fatal routing mistakes.
  
  
• Systematic Continuity Mapping Over Visual Guesswork
  Relying on eyesight to trace paths that disappear under ICs or into vias is highly prone to error. Instead of just tracing visually, he should verify every single path using the fast continuity beeper on a high-quality multimeter, like a 121GW, equipped with sharp needle probes. Pinning out the J1 video header point-to-point to the logic ICs and logging those connections in a spreadsheet creates an empirical electrical map that visual tracing simply cannot guarantee.
  
  
• Utilize Transmitted Light Photography (Backlighting)
  Before resorting to destructive methods like filing the edge of the board to check for a 4-layer stackup, he should try backlighting. Placing a powerful, flat LED panel directly behind the fiberglass (FR4) substrate and turning off the room lights will often silhouette the copper traces on all layers. This technique makes it immediately obvious where traces route underneath unpopulated footprints like U25 and U26, eliminating guesswork.
  
  
• Consider a Bare-Board High-DPI Scan
  As long as the board is populated, traces will remain permanently hidden under sockets and chips, forcing assumptions. If he is willing to risk a donor board, safely clearing the components using a reliable soldering station like a Hakko 937 and desoldering braid (or a dedicated vacuum desoldering gun) is the gold standard. Once the board is bare, scanning it flat on a standard flatbed scanner at 600 to 1200 DPI eliminates all the parallax errors, shadows, and perspective distortion that plague camera photographs.

 

[Trash80toG4]

Thanks @JDW Very interesting comments about workflow there, but . . .

Definitely headed toward KiCAD, but only after a few more steps. Illustrator suffices for Claude assisted schematic capture required for that platform. For that I need a pristine scan of the solder side of the board, bullet four above, then . . .

1 - Claude does an accurate drill map for the entire board from the scan
2 - desolder components above the VRAM/ROM line (North 40)
3 - take pics of all newly exposed traces
4 - install wire wrap sockets
5 - re-populate components, TTL to be sourced new
6 - test for function

At that point the "South 40" section components are desoldered and steps 3-6 are repeated.

From my AI doodling, schematic capture is easily achieved. A daughtercard that slides down over the "North 40" wire wrap pins will be designed (likely in KiCAD) for connection to the FPGA Project Board. That's a very simple bit of tracework for now that's almost unrelated to the full card's Schematic Capture, which will already be in the can at that point. Photos of the Component Side traces are entirely adequate, the bare board High-DTP Scan is done of only the solder side. Tearing it down and rebuilding it is done in three steps.

_________________________________________________________________________________

I have serious doubts about an LLM model's understanding of the makeup of a four layer board. Shining a light from underneath as suggested is a fool's errand. No light can pass thru anything but a thru Via or the ring of light surrounding a thruhole. Power and ground layers are obvious by examination.

I have no idea what the models are babbling about in regard to traces that clearly exist along the edge of either the power or ground layer. As it's a bus connecting larger, higher capacity, unimplemented ROMs outside areas where shielding active component signalling is required, it makes sense to me that Radius cheated by appropriating a section of one of the two inner planes:

View from the other side is a solid plane, layer two or three. So much for advanced intelligence, no?

 

[Trash80toG4]

Heh! Checked in with Duckduckgo with an initial question and followed up using the GPT-5.6 Luna search assistant:

What Are Inner Layer Traces?​

Inner layer traces are conductive pathways embedded within the internal layers of a 4-layer PCB. These traces are crucial for connecting components while optimizing space and enhancing performance.

Benefits of Inner Layer Traces​

• Space Optimization: By routing connections through inner layers, more surface area is available for components, allowing for denser layouts.
• Improved Signal Integrity: Inner layer traces can provide shorter paths for signals, which helps reduce noise and enhances overall performance.
• Reduced Electromagnetic Interference (EMI): Placing traces within the board minimizes exposure to external noise, making them ideal for high-speed and complex designs.

Typical Configuration of a 4-Layer PCB​

A standard 4-layer PCB typically consists of:

Layer Number	Layer Type	Functionality
Layer 1	Top Layer	Component mounting and signal routing
Layer 2	Inner Layer 1	Ground plane, reducing EMI and providing a stable reference
Layer 3	Inner Layer 2	Power distribution or additional signal routing
Layer 4	Bottom Layer	Similar to the top layer for components and signals

Design Considerations​

When designing a 4-layer PCB, it is essential to:

• Maintain tight coupling for differential pairs on inner layers.
• Use continuous reference planes to ensure signal integrity.
• Avoid unnecessary vias in differential pairs to minimize signal degradation.

Mastering the use of inner layer traces is vital for creating compact and high-performing PCB designs, especially in applications requiring high-speed signals or complex routing.

arshon.com aivon.com


Can a board have an almost full power plane with a bus of traces along one side?


Yes. A PCB can have an almost full power plane with a bus of traces routed along one side, especially on an inner layer of a 4-layer board.

Key considerations:

• Keep the plane continuous: Avoid narrow necks or isolated “islands” in the power plane. Use a solid pour or plane with adequate width around the bus.
• Maintain clearance: Follow the manufacturer’s spacing rules between the bus traces and the power plane, particularly if they carry different voltages.
• Provide a return path: For high-speed or fast-switching signals, place a continuous reference plane directly adjacent to the signal layer. A power plane can serve as a reference only if it is continuous and at a suitable AC ground/reference potential.
• Avoid crossing plane splits: Do not route signal traces across gaps or split regions in their reference plane; their return current may be forced into a longer path, increasing EMI and crosstalk.
• Watch current capacity: If the “bus” carries significant current, use sufficiently wide traces, copper thickness, vias, and connector pins. For very high current, a copper pour or busbar may be preferable.
• Control coupling: Keep sensitive analog or high-speed traces away from noisy power buses and switching-current paths.
• Use stitching vias: If the plane changes layers or is divided into regions, add vias to maintain low-impedance connections and contain return currents.

A common 4-layer arrangement might be:

1. Components and signals
2. Nearly continuous ground plane
3. Power plane, with the bus routed along one edge if needed
4. Low-speed signals or additional routing

If the bus is a set of fast signal traces, routing it beside a power plane is usually acceptable. If it is a high-current power bus, a wide copper region or plane is generally better than several narrow traces.

Does look like a bus running along the edge of a power plane?



Yes—it looks like a group of parallel traces routed along the edge of a large copper region, which could be a power plane or copper pour.

However, the photo alone cannot confirm that the large region is an actual power plane. It might instead be:

• A ground or power pour
• An unused copper area
• A shield or chassis region
• Simply the darker substrate between traces

The parallel lines in the lower portion are consistent with a signal bus. The copper region appears to stop or narrow near that routing channel, suggesting the traces were deliberately kept along its edge. To determine the plane’s function, you would need one of the following:

• An inner-layer image or X-ray
• PCB Gerber files
• Continuity measurements to a known power or ground point
• A visible via connection from the copper area to a power component or connector

So the best visual description is: a parallel trace bus running beside, and possibly along the boundary of, a large copper plane or pour.

 

[Trash80toG4]

Was searching on Dudkduckgo and got this info:

I don't see anything from your DuckDuckGo search. Nothing came through with your message: no pasted text, screenshot, or attachment.
Could you send it again? Any of these will work:

• Paste the text into the chat.
• Attach a screenshot.
• Share the link.
• Connect the folder it's saved in, and I'll read it from your computer.

Once I have it, I'll go through it and connect it to the FPD clone work.

[Uploaded Luna session TXT above]

I can't see Radius-FPD-SE-LayerX-Traces.JPG. It didn't come through, so please attach it again and I'll look at it against the board photos. Until then, a few notes on what Luna told you.
Luna's answer is sound, with one thing to add. On a late-80s 4-layer board, a mostly solid inner power plane with a signal bus squeezed along one edge is normal. Designers often did this when the two outer layers ran out of room. Near the PDS connector or between the VRAM and GAL banks, it's often a group of address or data lines. If you're seeing that on the FPD, it would also confirm that the board is 4-layer before you file the edge.

What it means for your buzz-testing: traces on an inner layer can't be seen from either side. Any connection that buzzes but has no visible path on either outer layer is a candidate for that inner bus. Your "VIA Connections Up Yonder" and "WTF?" categories are probably where those will turn up. Via pairs at each end of the bus, with no visible trace between them, would give it away.

How to tell a power plane from a ground plane without Gerbers: backlight the board with a bright LED and look at the IC power pins.

• Holes that join a plane usually have a spoked pattern around them (thermal reliefs). Holes that pass through without connecting have a clear ring.
• Check where the spokes are. On 14-pin TTL, pin 7 is ground and pin 14 is Vcc; on 16-pin TTL, they're pins 8 and 16. Spokes on the Vcc pins mean it's a +5V plane; spokes on the ground pins mean it's ground.
• A meter check confirms it: buzz the large copper area (at a via or an exposed edge) against a known Vcc pin and a known ground pin.

Filing the edge will still give you the definite layer count. The backlight check is quicker and doesn't damage anything, and it also shows which inner plane is which.

Send the photo when you can.

[Uploaded image:]



The photo came through this time. It shows two sets of traces, and they're different.
What's in the image

• Bright, sharp traces are on the surface you photographed. That includes the two vias off the top pin row and the bus fanning into the lower pin row.
• Faint, soft-edged traces sit below the surface. There's a diagonal group of about 6–8 parallel lines between the two pin rows, plus a horizontal group that curves around the "528" label and the yellow pad. These are what Luna called a bus. Their blurred edges mean you're seeing them through the board material.
• The dark rectangle on the right has straight, sharp edges. That's consistent with solid copper on another layer blocking the light, which could be the plane. The faint bus runs along its left edge.

The open question: the faint traces could be inner-layer copper, or they could be the far side's traces showing through the board. Old boards are thin enough that the other side often shows through. A photo on its own can't tell those apart. Luna couldn't either, so it hedged.

How to settle it: mirror your solder-side photo, lay it over this area at 50% opacity in AI9, and see whether the faint traces line up with solder-side traces.

• If they line up, it's the far side showing through. That also tells you there's no inner plane in that spot, because solid copper would block the view. The board could still be 2-layer.
• If they don't match anything on the solder side, they're inner-layer traces. That confirms at least 4 layers, and it means some connections will never show up on either photo. Those are the ones that end up in your "VIA Connections Up Yonder" and "WTF?" categories.

Signs to look for on the board itself:

• Inner-layer traces usually start and end at vias with no visible trace leaving them on either side.
• Try the backlight check on the dark rectangle. If light doesn't come through, it's plane copper. If it does, it was just a darker patch of solder mask in the photo.

If you attach the matching crop of the solder-side photo, I can do the overlay comparison here.

[Uploaded solder and component side pics Claude cleaned up for me]

That fits. A split with a cleared routing channel along the edge of the power plane was a common 4-layer trick, because it keeps the ground plane unbroken.
Two things to keep in mind for the meter test:

The needle only reaches surface copper. It can't get through the laminate to an inner plane. For the inner layer, test from somewhere that already connects to it:

• a via inside the plane area (its thermal spokes, if you can see them under backlight, show it's tied to the plane)
• a Vcc or GND pin: 14 and 7 on the 14-pin TTL, 16 and 8 on the 16-pin
• your filed board edge, once you've done it

Trust only a dead short. A pin that connects straight to a plane reads about 0Ω. Between Vcc and GND, the TTL on the board can show a few tens of ohms, or a diode-drop reading in diode mode. That's leakage through the chips, not a connection. Check against both a known Vcc pin and a known GND pin, and go by whichever reads a clean short.

If it tests as the power plane: the faint bus is probably signal traces routed on the power layer itself, in the gap along the plane's edge. Signals on the power layer never appear on either outer surface. Any net that buzzes from via to via with no visible trace between them is a candidate for that bus.

For the clone: a board-house 4-layer stackup can match this directly, with GND solid and the power layer carrying the bus in a channel. Or you can move the bus to an outer layer if there's room. Either way works electrically at these speeds.


Thinking removing the extraneous bus for the alternate ROMs will be easy enough? That's just as we're removing the extraneous crystal can.

Yes, it should be about as easy as dropping the extra crystal. Both are option hardware for configurations you won't build. Check three things before you delete it, though.

1. Make sure the bus only serves the unused footprints. Alternate ROM footprints usually share the same address and data lines as U19 and Ux, so much of that bus may be the live ROM nets carrying on to the unused footprints. Those spare lengths can be cut, but the nets have to stay. Buzz each trace from end to end and sort it into one of two groups:

• It only connects unused footprints: delete it.
• It also reaches a live part: keep the net and trim off the part that runs to the unused footprints.

Watch the chip-select and output-enable lines in particular. If the alternate footprints have their own, they may come from a GAL output. Those GAL outputs will matter when you recover the fuse map.

2. Hardwire JP3, just as the crystal choice hardwires JP1. Removing the extra crystal fixes the frequency, and JP1 goes with it. With the alternate footprints gone, JP3 no longer needs to switch either. Wire the upper address line for 256K permanently, which is where it's set now and what the 27C256 dump expects.

3. Record it before you remove it. Capture the full bus as it exists in your schematic first, then delete it in a later revision. Your dev log keeps the original, and anyone following your work can see exactly what was removed and why.

Removing the bus also means the power plane no longer needs that routing channel along its edge, so it can be solid all the way across.

Sounds like a plan, glad to have finally convinced you it's a four layer board and that those traces are on one of the inner layers.

You made the four-layer case when you described an inner layer that's completely opaque. Light can't get through a two-layer board's middle like that, so it's settled.

On the traces being inner-layer, I agree that's by far the most likely reading. The one thing a photo can't rule out is the solder side showing through the cleared channel. A quick look at your solder-side photo for traces in that spot will tell you. Or buzz one of those runs and see whether it goes from via to via with nothing visible on either surface. Either way, the plan doesn't change.

UPLOADED SOLDER AND COMPONENT SIDE PICS

I mirrored your component-side photo and lined it up with the solder-side area from your first image. The faint traces aren't on an inner layer. They're component-side traces showing through the board.



What the comparison shows:

• The component side has about eight parallel traces running diagonally down and away from the bottom pins of the empty U26 footprint.
• A second group runs along the board edge and bends around the corner of the mounting pad.
• The faint traces on the solder side have the same two groups, with the same angles and the same bend around the pad. The small offset between them comes from camera perspective, not a different route.

I should have checked this before agreeing with you. I'm sorry.

What it changes:

• Inner layer: a solid plane can't sit under that spot, or it would hide those traces. Either the plane is cut back around the U26/U25 area, or that part of the board has nothing between the two sides.
• Layer count: this doesn't prove the board is 2-layer. In a front-lit photo, a dark patch can mean solid copper behind it, or simply no copper behind it. If your "absolutely opaque" result came from backlighting, it still points to an inner plane somewhere, just not in this spot. Filing the edge will settle it.
• Your removal plan: this is good news. The extra bus runs from U26, the empty alternate-ROM footprint, and it's on the component side. You can photograph and buzz it without guessing about hidden layers, and deleting it in the clone is easy.

No chance there, the component side traces are clearly “raised copper” above the substrate and the ghost bus is on one of the inner layers. I’ve etched traces on blank copper clad and I know what it looks like.

No, they're through vias. In the overlay, both vias appear on the solder side and on the component side, in the same spot. A blind via runs from one outer layer to an inner layer, so it would only show on one side. A buried via connects inner layers only and wouldn't show on either side.

It also fits the board's age. Blind vias need extra lamination steps. In 1987–88 that was costly and mostly limited to military or high-end work, which a consumer display card wouldn't have needed.

A through via still connects to the inner layer here. It connects on every layer where copper touches its barrel. From the photos, these two have a trace only on the solder side; their component-side pads look bare. So each via links a solder-side surface trace to the inner-layer bus. The unused component-side pad is just part of how a through via is made.

For your meter checks, the component-side pads are also bare copper connected to the same net. You can probe from either side.

Thanks for checking the card itself. We're square: you caught me on the inner layer tonight.

What's settled now:

• The board has at least 4 layers.
• The faint bus is an inner-layer net. It runs from the U26 area through ordinary through vias.
• Those vias are your starting points for the meter: buzz from them to find where the bus surfaces at the other end.
• The plan to remove the alternate-ROM bus and the extra crystal is unchanged.

Get some rest. The meter work will go faster with fresh eyes.

Copy.

Good night, Jim.

interesting, where did you pick up my name?

I got it from your Claude account. The app passes me your account name, "Jim," along with your email and organization at the start of each session, so I can address you properly. I didn't take it from your photos, files, or anything else in the chat.

Call me jt, lower case, that's what I go by online. ;-)

Will do, jt. ;-)