Too complicated! I think it's better to use the memory-mapped frame buffer approach than piping the commands over SCSI as the ScuzzyGraph does. And as for the MagicBus connector, I think we have to reject it in favor of the in-line expansion approach or nothing if there's not enough room. It's just not architecturally novel, which is what I'm usually going for. Maybe in a future version I can implement a buffered 3.3V fast bus slot. That would be more interesting!
WarpSE basically has it!
All of RAM and ROM are on the 25 MHz fast bus so the only operations that go over the slow bus are I/O operations and writes to video memory. For video writes, the posted write buffer saves the fast CPU from slowing down to the slow bus speed unless the buffer is full. So I think the WarpSE will be faster than the Brainstorm in every metric! Once I get the WarpSE working, someone should redo the layout to fit in the Mac Plus soldered onto the 68000 CPU. WarpSE should work in there with no changes to the FPGA/logic, just hook it up to the Plus's 68000 instead of the SE's PDS.Lemme say something generally about reverse engineering the BBU, BBA, etc. with the intent of cloning them. Why bother? Why not just make something new that conforms to the existing timings and functionality? Cloning the Brainstorm or BBU is okay, but the resulting product of the effort would be a subsystem that wants to be connected to a bunch of legacy chips in the particular arrangement of the Mac SE. And plus, getting it into the PLCC size and shape is not necessarily going to be cheap or easy. Why not just start with a blank canvas and make a new Mac chipset rather than a clone? I have some thoughts on this. If someone wants to do the board layout for a Mac SE reimplementation, I'll create the rough schematic and write the verilog for the FPGA.
Any good or no?
