Ok, let me start over because I think we are getting crossed here
Indeed, but some of this doesn't make sense to me at all.
The LCIII supports 5 "Banks" (Banks may not be the correct technical term but it is what makes sense to me)
Per below, it would seem "Ranks" of memory would be more appropriate, no? With address lines contiguous between DRAM pads and SIMMs it looks more like just one Bank with 5 Ranks supported. Makes sense as Sonora is described as an amalgam of gubbins inherited from its LC grandpappy.
LCIII ROM is also born of the LC bloodline, which goes a long way toward explaining the ROM limitation of Rank A you're facing.
_____________________________________________________________________________________
Sonora Integrated Controller
Sonora is a new custom chip that integrates the functions of the V8 and SWIM chips used
in the Macintosh LC II. These functions include timing, memory mapping, video and
sound control, miscellaneous GLU (General Logic Unit) functions, and floppy disk
control. Sonora’s primary functions are described in the following sections.
______________________________________________________________________________________
LC475/Q605 generation represents a clean break from the LC development line with
MEMCjr as a pure Memory Controller with its roots in the Macintosh II line and
MDU. The extraneous gubbins present in
Sonora run through the
Prime Time ASIC.
Ok, let me start over because I think we are getting crossed here
Indeed, but some of this doesn't make sense to me at all.
The LCIII supports 5 "Banks" (Banks may not be the correct technical term but it is what makes sense to me)
Per below, it would seem "Ranks" of memory would be more appropriate, no? With address lines contiguous between DRAM pads and SIMMs it looks more like just one Bank with 5 Ranks supported. Makes sense as Sonora is described as an amalgam of gubbins inherited from its LC grandpappy.
LCIII ROM is also born of the LC bloodline, which goes a long way toward explaining the ROM limitation of Rank A you're facing.
_____________________________________________________________________________________
Sonora Integrated Controller
Sonora is a new custom chip that integrates the functions of the V8 and SWIM chips used
in the Macintosh LC II. These functions include timing, memory mapping, video and
sound control, miscellaneous GLU (General Logic Unit) functions, and floppy disk
control. Sonora’s primary functions are described in the following sections.
______________________________________________________________________________________
LC475/Q605 generation represents a clean break from the LC development line with
MEMCjr as a pure Memory Controller with its roots in the Macintosh II line and MDU. The extraneous gubbins present in Sonora run through the
Prime Time ASIC.
That's likely why LC475/Q605 can be expanded to stupid high memory levels by playing RAS line bodge games? It would appear to have two distinct Banks of memory making up its memory map topology?
Unified addressing of a 1 Bank memory map consisting of 5 Ranks in the map would be characteristic of the LC bloodline? Breaking the single SIMM, 16bit Bus bus bottleneck in the LC out into to a pair of 32bit SIMMs
Each Bank has one unique RAS line
Bank 0 is the onboard soldered RAM
Banks 1 and 2 are the 72pin simm socket
Banks 3 and 4 are the extra ones that are not normally used (But are fully functional)
This setup smacks of my Single Bank, 5 Rank memory map theory. I think we need to straighten out the terminology here by examining the topology of the memory map.
Again, do you have a utility that's reporting the system described above as existing in two distinct Banks of memory?
The unified 1 Bank, 5 Rank theory would be disproved by such reportage and I'd love to get my hands on that utility!
A0-9, CAS0-3 and D0-31 are connected across all banks
A10 is connected across banks 1 to 4
Yep, was following the wrong address line when I split A9 out across the DRAM ICs. Way too tired after recovering my lost work, did A10 up to where it bypasses the DRAM IC pads a bit ago.
Restart wasn't as bad as I'd thought it would be, AI's incremental saves were a blessing. Too tired to begin with, I should have been up to Rev. 002 of the file by my customary incremental saves. Was still 000 when the system froze. Duh'Oh!
A11 is not connected to any bank and dose not appear to be implemented by the sonora
Makes sense, again the LC architectural bodge lineage.
With A0-9 connected on bank 0 it gives a maximum possible memory capacity of 4MB. Installing higher capacity RAM and connecting A10 dose not increase how much the LCIII detects in this bank.
Definitely lost me with this one, A0-9 would be ten bits which should translate into 16MB supported, no?
It appears this is a ROM limitation and that the LCIII dose not size bank 0 and just assumes it is 4MB. Removing the RAM from this bank produces no chime, or chimes of death with simm in the simm socket reinforcing the fact the LCIII is not sizing bank 0 (
@cy384 is looking into patching the ROM to assume it has 16MB in bank 0)
Cool, hoping that's possible, as above there should be addressing available for Rank 0 in place on your adapter board.
With A0-10 connected on banks 1-3 this gives a maximum possible memory capacity of 16MB per bank. This is why 32MB sticks work fine in the LCIII (Remember the 32MB simms contains two "banks" of 16MB each) but 128MB simms are only recognised as 32MB.
Given the 1 Bank of 5 Ranks theory, this makes perfect sense outside of A0-10 being 11 bits supporting 32MB.
@trag can the 16MB per Rank limit be a function of CAS line implementation? RAS line and addressing don't make sense to me?
So as it stands the maximum possible memory that the LCIII can use with the stock ROM is 68MB (4MB in bank 0 and 16MB in banks 1-4) rising to 80MB (16MB in banks 0-4) if the ROM patching is successful
Again, banging my noggin on that addressing issue, Rank 0 has 10 of 12 possible address lines, so 16MB should be supported, no?
Getting more than 68/80MB would require A11 but this dose not appear to be implemented on the sonora
Yep, LC bodge lineage of Sonora makes perfect sense here. Again, Apple. Lash up the building blocks of the previous generation with duct tape and bailing wire to push the line as far as possible while following a different path for the following generation.
I may need a refresher course on how addressing works here.
ASIC.
That's likely why LC475/Q605 can be expanded to stupid high memory levels by playing RAS line bodge games?
Unified addressing of a 1 Bank memory map consisting of 5 Ranks in the map would be characteristic of the LC bloodline? Breaking the single SIMM, 16bit Bus bus bottleneck in the LC out into to a pair of 32bit SIMMs sounds like a real kluge?
Each Bank has one unique RAS line
Bank 0 is the onboard soldered RAM
Banks 1 and 2 are the 72pin simm socket
Banks 3 and 4 are the extra ones that are not normally used (But are fully functional)
This setup smacks of my Single Bank, 5 Rank memory map theory. I think we need to straighten out the terminology here by examining the topology of the memory map.
Again, do you have a utility that's reporting the system described above as existing in two distinct Banks of memory?
The unified 1 Bank, 5 Rank theory would be disproved by such reportage and I'd love to get my hands on that utility!
A0-9, CAS0-3 and D0-31 are connected across all banks
A10 is connected across banks 1 to 4
Yep, was following the wrong address line when I split A9 out across the DRAM ICs. Way too tired after recovering my lost work, did A10 up to where it bypasses the DRAM IC pads a bit ago.
Restart wasn't as bad as I'd thought it would be, AI's incremental saves were a blessing. Too tired to begin with, I should have been up to Rev. 002 of the file by my customary incremental saves. Was still 000 when the system froze. Duh'Oh!
A11 is not connected to any bank and dose not appear to be implemented by the sonora
Makes sense, again the LC architectural bodge lineage.
With A0-9 connected on bank 0 it gives a maximum possible memory capacity of 4MB. Installing higher capacity RAM and connecting A10 dose not increase how much the LCIII detects in this bank.
Definitely lost me with this one, A0-9 would be ten bits which should translate into 16MB supported, no?
It appears this is a ROM limitation and that the LCIII dose not size bank 0 and just assumes it is 4MB. Removing the RAM from this bank produces no chime, or chimes of death with simm in the simm socket reinforcing the fact the LCIII is not sizing bank 0 (
@cy384 is looking into patching the ROM to assume it has 16MB in bank 0)
Cool, hoping that's possible, as above there should be addressing available for Rank 0 in place on your adapter board.
With A0-10 connected on banks 1-3 this gives a maximum possible memory capacity of 16MB per bank. This is why 32MB sticks work fine in the LCIII (Remember the 32MB simms contains two "banks" of 16MB each) but 128MB simms are only recognised as 32MB.
Given the 1 Bank of 5 Ranks theory, this makes perfect sense outside of A0-10 being 11 bits supporting 32MB.
@trag can the 16MB per Rank limit be a function of CAS line implementation? RAS line and addressing don't make sense to me?
So as it stands the maximum possible memory that the LCIII can use with the stock ROM is 68MB (4MB in bank 0 and 16MB in banks 1-4) rising to 80MB (16MB in banks 0-4) if the ROM patching is successful
Again, banging my noggin on that addressing issue, Rank 0 has 10 of 12 possible address lines, so 16MB should be supported, no?
Getting more than 68/80MB would require A11 but this dose not appear to be implemented on the sonora
Yep, LC bodge lineage of Sonora makes perfect sense here. Again, Apple. Lash up the building blocks of the previous generation with duct tape and bailing wire to push the line as far as possible while following a different path for the following generation.
I may need a refresher course on how addressing works here. My limited understanding comes from working backwards from 12 bits needed for addressing 64MB in MDU systems.
@trag and you are working your way up the ladder via steps in maths beyond my ken.