Breaking the 36MB RAM limit on the LCIII
- Thread starter max1zzz
- Start date
Found this diagram of MDU memory controller from the IIsi and IIci in my backup of MLA attachments:
Note how Addressing for Bank A (DRAM ICs) and Bank B (SIMMs) are discrete connections to each Memory Bank.
That's been my concern, if anything like that is going on in the Sonora Memory Controller pinout, I don't think you're addressing the problem correctly . . . so to speak.
Note how Addressing for Bank A (DRAM ICs) and Bank B (SIMMs) are discrete connections to each Memory Bank.
That's been my concern, if anything like that is going on in the Sonora Memory Controller pinout, I don't think you're addressing the problem correctly . . . so to speak.
OK, been looking at this as a plumbing diagram, continuity testing would be the way to go. Haven't gotten any further in my refresher read, but hoping this is still the case. You're still using this adapter in testing?
If I'm understanding it correctly, you designed this adapter for the case that:
Address lines A0-A9***** are contiguous between Bank A and Bank B
- - do all (or any) address lines present continuity between Banks A & B?
- - - Bank A soldered DRAM requires fewer Address lines than Bank B
***** Not sure we're using the same nomenclature here, trag said we need to be careful about that. Per BOMARC, MDU utilizes twelve address lines: A0-A11 to support 64MB in Bank B. So in the IIsi I only need A11 to round it out to the full 12 lines. You've been saying we need 11 address lines to get where you'd like to go? That'd be A0 - A10 so I'm a tad confused here?
At any rate, continuity testing between Bank A DRAM and the three SIMM slots may tell the tale?
Again: Occam insists that any memory limitation in ROM would be applied to Bank B as, once more, Bank A is limited by trace count to soldered DRAM. You've proven the case that expansion to 64MB in bank B is possible. That's where the limitation in ROM was placed for the LC's 10MB ceiling. By inference, that would be the case for a ROM limitation in the LCIII? There's no need for such a limitation as it's implemented in the PCB design of the logic board?
Is there an available schematic for the LC or the LCIII? IIRC, DevNote for the LC is unobtanium? Is IF there's a ROM limitation
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< tangent mode >
Can't help myself, morning musing mode strikes again, gobbledegook warning:
You've got me wondering, is LC soldered and SIMM memory wired up on the Logic Board as a single bank, two, three or four Banks of Memory? Seems unlikely, but if implemented in any case, Occam insists that 10MB limitation would be done in trace count of address lines implemented from Memory Controller to the two SIMM Slots on the Logic Board. Soldered DRAM is limited in that manner. IF so, THEN ROM limitation would be necessary only for the subset of Banks implemented in SIMM slot? Doing the limitation in ROM is unnecessary if done at the Logic Board level. Even if done in ROM for the SIMM Slots, Limitation for soldered memory would not be necessary.
Is the 10 MB limitation of LC inferred from observation/LEMlegend or a KNOWN from examination of ROM?
IOW, can the 10MB ceiling of the LC be attacked on the same Bank A front at IIsi and LCIII?
Sixteen bit memory bus complications are now hurting what I use for a brain.
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sTAYED HOME WITH A BUG TODAY AND HAD THIS BUG . . . (%&(&(*#& cAPSlOCK!!!!!
Playtime in AI:
Address lines are indeed contiguous between the Soldered DRAM and SIMM. Saw that right off, but felt like seeing the whole picture so I kept at it..
Strange that A0-A10 are implemented in Bank A, that's eleven lines, only one missing is the black hole that is A11. Bank A in the IIsi only has A0-A9 implemented, very strange. Then again 1MB is all that needs to be addressed in that machine. I'll follow traces from CAS and RAS pins to see what's up next I guess.
What are the specs on DRAM ICs and what looks to be buffering where I lost the trail of A10?
Playtime in AI:
Address lines are indeed contiguous between the Soldered DRAM and SIMM. Saw that right off, but felt like seeing the whole picture so I kept at it..
Strange that A0-A10 are implemented in Bank A, that's eleven lines, only one missing is the black hole that is A11. Bank A in the IIsi only has A0-A9 implemented, very strange. Then again 1MB is all that needs to be addressed in that machine. I'll follow traces from CAS and RAS pins to see what's up next I guess.
What are the specs on DRAM ICs and what looks to be buffering where I lost the trail of A10?
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Ok, let me start over because I think we are getting crossed here
The LCIII supports 5 "Banks" (Banks may not be the correct technical term but it is what makes sense to me)
Each Bank has one unique RAS line
Bank 0 is the onboard soldered RAM
Banks 1 and 2 are the 72pin simm socket
Banks 3 and 4 are the extra ones that are not normally used (But are fully functional)
A0-9, CAS0-3 and D0-31 are connected across all banks
A10 is connected across banks 1 to 4
A11 is not connected to any bank and dose not appear to be implemented by the sonora
With A0-9 connected on bank 0 it gives a maximum possible memory capacity of 4MB. Installing higher capacity RAM and connecting A10 dose not increase how much the LCIII detects in this bank. It appears this is a ROM limitation and that the LCIII dose not size bank 0 and just assumes it is 4MB. Removing the RAM from this bank produces no chime, or chimes of death with simm in the simm socket reinforcing the fact the LCIII is not sizing bank 0 (@cy384 is looking into patching the ROM to assume it has 16MB in bank 0)
With A0-10 connected on banks 1-3 this gives a maximum possible memory capacity of 16MB per bank. This is why 32MB sticks work fine in the LCIII (Remember the 32MB simms contains two "banks" of 16MB each) but 128MB simms are only recognised as 32MB.
So as it stands the maximum possible memory that the LCIII can use with the stock ROM is 68MB (4MB in bank 0 and 16MB in banks 1-4) rising to 80MB (16MB in banks 0-4) if the ROM patching is successful
Getting more than 68/80MB would require A11 but this dose not appear to be implemented on the sonora
The LCIII supports 5 "Banks" (Banks may not be the correct technical term but it is what makes sense to me)
Each Bank has one unique RAS line
Bank 0 is the onboard soldered RAM
Banks 1 and 2 are the 72pin simm socket
Banks 3 and 4 are the extra ones that are not normally used (But are fully functional)
A0-9, CAS0-3 and D0-31 are connected across all banks
A10 is connected across banks 1 to 4
A11 is not connected to any bank and dose not appear to be implemented by the sonora
With A0-9 connected on bank 0 it gives a maximum possible memory capacity of 4MB. Installing higher capacity RAM and connecting A10 dose not increase how much the LCIII detects in this bank. It appears this is a ROM limitation and that the LCIII dose not size bank 0 and just assumes it is 4MB. Removing the RAM from this bank produces no chime, or chimes of death with simm in the simm socket reinforcing the fact the LCIII is not sizing bank 0 (@cy384 is looking into patching the ROM to assume it has 16MB in bank 0)
With A0-10 connected on banks 1-3 this gives a maximum possible memory capacity of 16MB per bank. This is why 32MB sticks work fine in the LCIII (Remember the 32MB simms contains two "banks" of 16MB each) but 128MB simms are only recognised as 32MB.
So as it stands the maximum possible memory that the LCIII can use with the stock ROM is 68MB (4MB in bank 0 and 16MB in banks 1-4) rising to 80MB (16MB in banks 0-4) if the ROM patching is successful
Getting more than 68/80MB would require A11 but this dose not appear to be implemented on the sonora
Indeed, but some of this doesn't make sense to me at all.
Per below, it would seem "Ranks" of memory would be more appropriate, no? With address lines contiguous between DRAM pads and SIMMs it looks more like just one Bank with 5 Ranks supported. Makes sense as Sonora is described as an amalgam of gubbins inherited from its LC grandpappy.
LCIII ROM is also born of the LC bloodline, which goes a long way toward explaining the ROM limitation of Rank A you're facing.
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Sonora Integrated Controller
Sonora is a new custom chip that integrates the functions of the V8 and SWIM chips used
in the Macintosh LC II. These functions include timing, memory mapping, video and
sound control, miscellaneous GLU (General Logic Unit) functions, and floppy disk
control. Sonora’s primary functions are described in the following sections.
______________________________________________________________________________________
LC475/Q605 generation represents a clean break from the LC development line with MEMCjr as a pure Memory Controller with its roots in the Macintosh II line and MDU. The extraneous gubbins present in Sonora run through the Prime Time ASIC.
Indeed, but some of this doesn't make sense to me at all.
Per below, it would seem "Ranks" of memory would be more appropriate, no? With address lines contiguous between DRAM pads and SIMMs it looks more like just one Bank with 5 Ranks supported. Makes sense as Sonora is described as an amalgam of gubbins inherited from its LC grandpappy.
LCIII ROM is also born of the LC bloodline, which goes a long way toward explaining the ROM limitation of Rank A you're facing.
_____________________________________________________________________________________
Sonora Integrated Controller
Sonora is a new custom chip that integrates the functions of the V8 and SWIM chips used
in the Macintosh LC II. These functions include timing, memory mapping, video and
sound control, miscellaneous GLU (General Logic Unit) functions, and floppy disk
control. Sonora’s primary functions are described in the following sections.
______________________________________________________________________________________
LC475/Q605 generation represents a clean break from the LC development line with MEMCjr as a pure Memory Controller with its roots in the Macintosh II line and MDU. The extraneous gubbins present in Sonora run through the Prime Time ASIC.
That's likely why LC475/Q605 can be expanded to stupid high memory levels by playing RAS line bodge games? It would appear to have two distinct Banks of memory making up its memory map topology?
Unified addressing of a 1 Bank memory map consisting of 5 Ranks in the map would be characteristic of the LC bloodline? Breaking the single SIMM, 16bit Bus bus bottleneck in the LC out into to a pair of 32bit SIMMs
This setup smacks of my Single Bank, 5 Rank memory map theory. I think we need to straighten out the terminology here by examining the topology of the memory map.
Again, do you have a utility that's reporting the system described above as existing in two distinct Banks of memory?
The unified 1 Bank, 5 Rank theory would be disproved by such reportage and I'd love to get my hands on that utility!
Yep, was following the wrong address line when I split A9 out across the DRAM ICs. Way too tired after recovering my lost work, did A10 up to where it bypasses the DRAM IC pads a bit ago.
Restart wasn't as bad as I'd thought it would be, AI's incremental saves were a blessing. Too tired to begin with, I should have been up to Rev. 002 of the file by my customary incremental saves. Was still 000 when the system froze. Duh'Oh!
Makes sense, again the LC architectural bodge lineage.
Definitely lost me with this one, A0-9 would be ten bits which should translate into 16MB supported, no?
Cool, hoping that's possible, as above there should be addressing available for Rank 0 in place on your adapter board.
Given the 1 Bank of 5 Ranks theory, this makes perfect sense outside of A0-10 being 11 bits supporting 32MB. @trag can the 16MB per Rank limit be a function of CAS line implementation? RAS line and addressing don't make sense to me?
Again, banging my noggin on that addressing issue, Rank 0 has 10 of 12 possible address lines, so 16MB should be supported, no?
Yep, LC bodge lineage of Sonora makes perfect sense here. Again, Apple. Lash up the building blocks of the previous generation with duct tape and bailing wire to push the line as far as possible while following a different path for the following generation.
I may need a refresher course on how addressing works here.
ASIC.
That's likely why LC475/Q605 can be expanded to stupid high memory levels by playing RAS line bodge games?
Unified addressing of a 1 Bank memory map consisting of 5 Ranks in the map would be characteristic of the LC bloodline? Breaking the single SIMM, 16bit Bus bus bottleneck in the LC out into to a pair of 32bit SIMMs sounds like a real kluge?
This setup smacks of my Single Bank, 5 Rank memory map theory. I think we need to straighten out the terminology here by examining the topology of the memory map.
Again, do you have a utility that's reporting the system described above as existing in two distinct Banks of memory?
The unified 1 Bank, 5 Rank theory would be disproved by such reportage and I'd love to get my hands on that utility!
Yep, was following the wrong address line when I split A9 out across the DRAM ICs. Way too tired after recovering my lost work, did A10 up to where it bypasses the DRAM IC pads a bit ago.
Restart wasn't as bad as I'd thought it would be, AI's incremental saves were a blessing. Too tired to begin with, I should have been up to Rev. 002 of the file by my customary incremental saves. Was still 000 when the system froze. Duh'Oh!
Makes sense, again the LC architectural bodge lineage.
Definitely lost me with this one, A0-9 would be ten bits which should translate into 16MB supported, no?
Cool, hoping that's possible, as above there should be addressing available for Rank 0 in place on your adapter board.
Given the 1 Bank of 5 Ranks theory, this makes perfect sense outside of A0-10 being 11 bits supporting 32MB. @trag can the 16MB per Rank limit be a function of CAS line implementation? RAS line and addressing don't make sense to me?
Again, banging my noggin on that addressing issue, Rank 0 has 10 of 12 possible address lines, so 16MB should be supported, no?
Yep, LC bodge lineage of Sonora makes perfect sense here. Again, Apple. Lash up the building blocks of the previous generation with duct tape and bailing wire to push the line as far as possible while following a different path for the following generation.
I may need a refresher course on how addressing works here. My limited understanding comes from working backwards from 12 bits needed for addressing 64MB in MDU systems. @trag and you are working your way up the ladder via steps in maths beyond my ken.
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Yes probably, I only say "banks" as that is what is logical to me even though it is probably technically incorrect . From here on in we shall refer to them as "Ranks"
Don't know why I keep not answering that - no I don't. I'm purley working on what About this Mac reports, I think the confusion here goes back tot he "Banks v Ranks thing"
For this i'm gonna quote @trag's post for earlier in the thread:
So if we take all that with 10 address bits (A0-9) we get:
2^20 = 1M of unique adresses
1M x 4Bytes = 4MB
It confused me for ages too it seems logical addressable memory should double with each address line added but as they are multiplexed it actually quadruples
And while where here, here is a custom quad rank SIMM for the LCIII:
32 RAM IC's was quite a lot to squeeze ona 72pin simm!
Just have to hope it's not going to be too tall to fit in the case now!
32 RAM IC's was quite a lot to squeeze ona 72pin simm!
Just have to hope it's not going to be too tall to fit in the case now!
And while where here, here is a custom quad rank SIMM for the LCIII:
View attachment 6590
32 RAM IC's was quite a lot to squeeze ona 72pin simm!
Just have to hope it's not going to be too tall to fit in the case now!
IC's all on one side?
16 on each sideIC's all on one side?
(It just looks like there is nothing on the other side as the chips are sitting exactly on top or each other)
Way cool, max!. Looks like it might fit. Print it out at actual size, rubber cement the paper to cardboard, cut it out, stick it in the slot and measure clearance. Haven't got an LC case handy, but if it's equal to or shorter than the FDD you should be good to go.32 RAM IC's was quite a lot to squeeze ona 72pin simm!
Just have to hope it's not going to be too tall to fit in the case now!
If it doesn't fit, the diagram I drew upthread should work for fitting a pair of SIMMs/slots on a carrier SIMM card parallel to the logic board. You were looking at it backwards, thinking connectors might be in the way, but look again, it overhangs the DRAM ICs.
Cool! Can't ask for more than that.Yes probably, I only say "banks" as that is what is logical to me even though it is probably technically incorrect . From here on in we shall refer to them as "Ranks"
Yep, that cropped up a month or two ago in the MLA PM thread I think.
< waves white flag furiously >You're way ahead of me on that stuff . . . see above.
Cannot believe you've had any time at all for this what with the arrival of PCBs yesterday:
Cloning the Interware Booster 30
Thankfully I've got AI This way madness lies, just sayin' :-D
68kmla.org
You rock, my friend!
Looking at MegaSIMM3, I'm wondering if the bottom row of ICs might be interfering with the backside of the SIMM connector?
You all have a double life at other forums?just wondering, would it not be handy to have a sim with an adapter to a bandcable or pcb edgeconnector?
And if that does not exist, just solder on a bandcable, and make a strainrelease onto the pcb’s?
That way the megasim can find a spot anywhere is sufficiënt space.
32 RAM IC's was quite a lot to squeeze ona 72pin simm!
Just have to hope it's not going to be too tall to fit in the case now!
This is the way!
I think most here, definitely the founders, have or have been active members of the MLA.
Cable introduces too many problems at RAM access clocks. Works for NuBusexpansion at 10MHz.
@max1zzz named it GhostSIMM already, GhostSIMM III which is more appropriate. My nick for it was tongue in cheek commentary its SuperSized order of DRAM ICs.That way the megasim can find a spot anywhere is sufficiënt space.
Not really - some of us migrated entirely away from other forums when TD came into being
Just in case height limitations bites your butt, I just had myself a blast playing in GraphicConverter on the Lombard.32 RAM IC's was quite a lot to squeeze ona 72pin simm!
Just have to hope it's not going to be too tall to fit in the case now!
As your custom SIMM would be rotated 180 degrees in this configuration, any fli -floppery would be done on the riser card which could be higher. If there's interference with the ICs on the backside of the SIMM with the Socket you have more room to spread the chips out a bit.
edit: oopsie! forgot to add the ICs to the underside.
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Well, I must be lucky/happy then …..to have found you all here together
…thanks trash80 for the clarification above…..
As youall here do know much about the LCIII, (and other models) and my knowledge is very limited in that matter…
On this LCIII I am recapping (today)…I have a short (perhaps) offtopic question.
Its possible to get it running at 33Mhz as I understand.
Does it matter what/which speed coprocessor is installed?
What model should I search for?
The other question is if this mod would be worthwhile or make a big difference.
Specially later in combination with the new to be Ghost-Maxizzim
Any usable input is appreciated!